/*
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*
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* (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
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*
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* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#include <watchdog.h>
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#include <power/pmic.h>
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#include <fsl_pmic.h>
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#include <errno.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_SPL_BUILD
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void board_init_f(ulong bootflag)
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{
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/*
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* copy ourselves from where we are running to where we were
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* linked at. Use ulong pointers as all addresses involved
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* are 4-byte-aligned.
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*/
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ulong *start_ptr, *end_ptr, *link_ptr, *run_ptr, *dst;
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asm volatile ("ldr %0, =_start" : "=r"(start_ptr));
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asm volatile ("ldr %0, =_end" : "=r"(end_ptr));
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asm volatile ("ldr %0, =board_init_f" : "=r"(link_ptr));
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asm volatile ("adr %0, board_init_f" : "=r"(run_ptr));
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for (dst = start_ptr; dst < end_ptr; dst++)
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*dst = *(dst+(run_ptr-link_ptr));
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/*
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* branch to nand_boot's link-time address.
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*/
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asm volatile("ldr pc, =nand_boot");
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}
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#endif
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int dram_init(void)
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{
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/* dram_init must store complete ramsize in gd->ram_size */
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gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
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PHYS_SDRAM_1_SIZE);
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return 0;
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}
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int board_early_init_f(void)
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{
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/* CS5: CPLD incl. network controller */
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static const struct mxc_weimcs cs5 = {
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/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
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CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3),
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/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
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CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1),
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/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
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CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0)
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};
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mxc_setup_weimcs(5, &cs5);
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/* Setup UART1 and SPI2 pins */
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mx31_uart1_hw_init();
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mx31_spi2_hw_init();
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return 0;
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}
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int board_init(void)
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{
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/* adress of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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return 0;
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}
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int board_late_init(void)
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{
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u32 val;
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struct pmic *p;
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int ret;
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ret = pmic_init(CONFIG_FSL_PMIC_BUS);
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if (ret)
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return ret;
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p = pmic_get("FSL_PMIC");
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if (!p)
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return -ENODEV;
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/* Enable RTC battery */
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pmic_reg_read(p, REG_POWER_CTL0, &val);
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pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN);
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pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI);
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#ifdef CONFIG_HW_WATCHDOG
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hw_watchdog_init();
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#endif
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return 0;
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}
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int checkboard(void)
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{
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printf("Board: MX31PDK\n");
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_SMC911X
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rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
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#endif
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return rc;
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}
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