/*
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* Copyright 2009 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr_dimm_params.h>
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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/*
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* Factors to consider for clock adjust:
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* - number of chips on bus
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* - position of slot
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* - DDR1 vs. DDR2?
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* - ???
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*
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* This needs to be determined on a board-by-board basis.
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* 0110 3/4 cycle late
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* 0111 7/8 cycle late
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*/
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popts->clk_adjust = 4;
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/*
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* Factors to consider for CPO:
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* - frequency
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* - ddr1 vs. ddr2
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*/
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popts->cpo_override = 0xff;
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/*
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* Factors to consider for write data delay:
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* - number of DIMMs
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*
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* 1 = 1/4 clock delay
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* 2 = 1/2 clock delay
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* 3 = 3/4 clock delay
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* 4 = 1 clock delay
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* 5 = 5/4 clock delay
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* 6 = 3/2 clock delay
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*/
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popts->write_data_delay = 2;
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/*
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* Enable half drive strength
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*/
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popts->half_strength_driver_enable = 1;
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/* Write leveling override */
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popts->wrlvl_en = 1;
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popts->wrlvl_override = 1;
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popts->wrlvl_sample = 0xa;
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popts->wrlvl_start = 0x4;
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/* Rtt and Rtt_W override */
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popts->rtt_override = 1;
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popts->rtt_override_value = DDR3_RTT_60_OHM;
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popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
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}
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