/*
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* Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _FPGA_MANAGER_H_
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#define _FPGA_MANAGER_H_
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#include <altera.h>
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#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
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#include <asm/arch/fpga_manager_gen5.h>
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#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
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#include <asm/arch/fpga_manager_arria10.h>
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#endif
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/* FPGA CD Ratio Value */
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#define CDRATIO_x1 0x0
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#define CDRATIO_x2 0x1
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#define CDRATIO_x4 0x2
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#define CDRATIO_x8 0x3
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#ifndef __ASSEMBLY__
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/* Common prototypes */
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int fpgamgr_get_mode(void);
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int fpgamgr_poll_fpga_ready(void);
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void fpgamgr_program_write(const void *rbf_data, size_t rbf_size);
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int fpgamgr_test_fpga_ready(void);
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int fpgamgr_dclkcnt_set(unsigned long cnt);
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#endif /* __ASSEMBLY__ */
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#endif /* _FPGA_MANAGER_H_ */
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