/*
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* Copyright (C) 2011
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _DV_PLL_DEFS_H_
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#define _DV_PLL_DEFS_H_
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struct dv_pll_regs {
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unsigned int pid; /* 0x00 */
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unsigned char rsvd0[224]; /* 0x04 */
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unsigned int rstype; /* 0xe4 */
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unsigned char rsvd1[24]; /* 0xe8 */
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unsigned int pllctl; /* 0x100 */
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unsigned char rsvd2[4]; /* 0x104 */
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unsigned int secctl; /* 0x108 */
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unsigned int rv; /* 0x10c */
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unsigned int pllm; /* 0x110 */
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unsigned int prediv; /* 0x114 */
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unsigned int plldiv1; /* 0x118 */
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unsigned int plldiv2; /* 0x11c */
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unsigned int plldiv3; /* 0x120 */
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unsigned int oscdiv1; /* 0x124 */
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unsigned int postdiv; /* 0x128 */
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unsigned int bpdiv; /* 0x12c */
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unsigned char rsvd5[8]; /* 0x130 */
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unsigned int pllcmd; /* 0x138 */
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unsigned int pllstat; /* 0x13c */
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unsigned int alnctl; /* 0x140 */
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unsigned int dchange; /* 0x144 */
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unsigned int cken; /* 0x148 */
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unsigned int ckstat; /* 0x14c */
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unsigned int systat; /* 0x150 */
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unsigned char rsvd6[12]; /* 0x154 */
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unsigned int plldiv4; /* 0x160 */
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unsigned int plldiv5; /* 0x164 */
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unsigned int plldiv6; /* 0x168 */
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unsigned int plldiv7; /* 0x16C */
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unsigned int plldiv8; /* 0x170 */
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unsigned int plldiv9; /* 0x174 */
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};
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#define PLL_MASTER_LOCK (1 << 4)
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#define PLLCTL_CLOCK_MODE_SHIFT 8
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#define PLLCTL_PLLEN (1 << 0)
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#define PLLCTL_PLLPWRDN (1 << 1)
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#define PLLCTL_PLLRST (1 << 3)
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#define PLLCTL_PLLDIS (1 << 4)
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#define PLLCTL_PLLENSRC (1 << 5)
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#define PLLCTL_RES_9 (1 << 8)
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#define PLLCTL_EXTCLKSRC (1 << 9)
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#define PLL_DIVEN (1 << 15)
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#define PLL_POSTDEN PLL_DIVEN
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#define PLL_SCSCFG3_DIV45PENA (1 << 2)
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#define PLL_SCSCFG3_EMA_CLKSRC (1 << 1)
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#define PLL_RSTYPE_POR (1 << 0)
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#define PLL_RSTYPE_XWRST (1 << 1)
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#define PLLSECCTL_TINITZ (1 << 16)
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#define PLLSECCTL_TENABLE (1 << 17)
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#define PLLSECCTL_TENABLEDIV (1 << 18)
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#define PLLSECCTL_STOPMODE (1 << 22)
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#define PLLCMD_GOSET (1 << 0)
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#define PLLCMD_GOSTAT (1 << 0)
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#define PLL0_LOCK 0x07000000
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#define PLL1_LOCK 0x07000000
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#define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE)
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#define dv_pll1_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL1_BASE)
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#define ARM_PLLDIV (offsetof(struct dv_pll_regs, plldiv2))
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#define DDR_PLLDIV (offsetof(struct dv_pll_regs, plldiv7))
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#define SPI_PLLDIV (offsetof(struct dv_pll_regs, plldiv4))
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unsigned int davinci_clk_get(unsigned int div);
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#endif /* _DV_PLL_DEFS_H_ */
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