/*
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* Copyright (C) 2011
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _DV_AINTC_DEFS_H_
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#define _DV_AINTC_DEFS_H_
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struct dv_aintc_regs {
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unsigned int fiq0; /* 0x00 */
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unsigned int fiq1; /* 0x04 */
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unsigned int irq0; /* 0x08 */
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unsigned int irq1; /* 0x0c */
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unsigned int fiqentry; /* 0x10 */
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unsigned int irqentry; /* 0x14 */
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unsigned int eint0; /* 0x18 */
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unsigned int eint1; /* 0x1c */
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unsigned int intctl; /* 0x20 */
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unsigned int eabase; /* 0x24 */
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unsigned char rsvd0[8]; /* 0x28 */
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unsigned int intpri0; /* 0x30 */
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unsigned int intpri1; /* 0x34 */
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unsigned int intpri2; /* 0x38 */
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unsigned int intpri3; /* 0x3c */
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unsigned int intpri4; /* 0x40 */
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unsigned int intpri5; /* 0x44 */
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unsigned int intpri6; /* 0x48 */
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unsigned int intpri7; /* 0x4c */
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};
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#define dv_aintc_regs ((struct dv_aintc_regs *)DAVINCI_ARM_INTC_BASE)
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#define DV_AINTC_INTCTL_IDMODE (1 << 2)
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#endif /* _DV_AINTC_DEFS_H_ */
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