/*
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* SoC-specific code for tms320dm644x chips
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*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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* Copyright (C) 2008 Lyrtech <www.lyrtech.com>
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* Copyright (C) 2004 Texas Instruments.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/hardware.h>
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#define PINMUX0_EMACEN (1 << 31)
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#define PINMUX0_AECS5 (1 << 11)
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#define PINMUX0_AECS4 (1 << 10)
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#define PINMUX1_I2C (1 << 7)
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#define PINMUX1_UART1 (1 << 1)
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#define PINMUX1_UART0 (1 << 0)
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void davinci_enable_uart0(void)
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{
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lpsc_on(DAVINCI_LPSC_UART0);
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/* Bringup UART0 out of reset */
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REG(UART0_PWREMU_MGMT) = 0x00006001;
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/* Enable UART0 MUX lines */
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REG(PINMUX1) |= PINMUX1_UART0;
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}
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#ifdef CONFIG_DRIVER_TI_EMAC
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void davinci_enable_emac(void)
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{
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lpsc_on(DAVINCI_LPSC_EMAC);
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lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
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lpsc_on(DAVINCI_LPSC_MDIO);
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/* Enable GIO3.3V cells used for EMAC */
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REG(VDD3P3V_PWDN) = 0;
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/* Enable EMAC. */
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REG(PINMUX0) |= PINMUX0_EMACEN;
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}
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#endif
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#ifdef CONFIG_SYS_I2C_DAVINCI
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void davinci_enable_i2c(void)
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{
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lpsc_on(DAVINCI_LPSC_I2C);
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/* Enable I2C pin Mux */
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REG(PINMUX1) |= PINMUX1_I2C;
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}
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#endif
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void davinci_errata_workarounds(void)
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{
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/*
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* Workaround for TMS320DM6446 errata 1.3.22:
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* PSC: PTSTAT Register Does Not Clear After Warm/Maximum Reset
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* Revision(s) Affected: 1.3 and earlier
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*/
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REG(PSC_SILVER_BULLET) = 0;
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/*
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* Set the PR_OLD_COUNT bits in the Bus Burst Priority Register (PBBPR)
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* as suggested in TMS320DM6446 errata 2.1.2:
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*
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* On DM6446 Silicon Revision 2.1 and earlier, under certain conditions
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* low priority modules can occupy the bus and prevent high priority
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* modules like the VPSS from getting the required DDR2 throughput.
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* A hex value of 0x20 should provide a good ARM (cache enabled)
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* performance and still allow good utilization by the VPSS or other
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* modules.
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*/
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REG(VBPR) = 0x20;
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}
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