/*
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* Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef AT91_TC_H
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#define AT91_TC_H
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typedef struct at91_tcc {
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u32 ccr; /* 0x00 Channel Control Register */
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u32 cmr; /* 0x04 Channel Mode Register */
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u32 reserved1[2];
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u32 cv; /* 0x10 Counter Value */
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u32 ra; /* 0x14 Register A */
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u32 rb; /* 0x18 Register B */
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u32 rc; /* 0x1C Register C */
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u32 sr; /* 0x20 Status Register */
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u32 ier; /* 0x24 Interrupt Enable Register */
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u32 idr; /* 0x28 Interrupt Disable Register */
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u32 imr; /* 0x2C Interrupt Mask Register */
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u32 reserved3[4];
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} at91_tcc_t;
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#define AT91_TC_CCR_CLKEN 0x00000001
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#define AT91_TC_CCR_CLKDIS 0x00000002
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#define AT91_TC_CCR_SWTRG 0x00000004
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#define AT91_TC_CMR_CPCTRG 0x00004000
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#define AT91_TC_CMR_TCCLKS_CLOCK1 0x00000000
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#define AT91_TC_CMR_TCCLKS_CLOCK2 0x00000001
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#define AT91_TC_CMR_TCCLKS_CLOCK3 0x00000002
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#define AT91_TC_CMR_TCCLKS_CLOCK4 0x00000003
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#define AT91_TC_CMR_TCCLKS_CLOCK5 0x00000004
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#define AT91_TC_CMR_TCCLKS_XC0 0x00000005
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#define AT91_TC_CMR_TCCLKS_XC1 0x00000006
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#define AT91_TC_CMR_TCCLKS_XC2 0x00000007
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typedef struct at91_tc {
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at91_tcc_t tc[3]; /* 0x00 TC Channel 0-2 */
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u32 bcr; /* 0xC0 TC Block Control Register */
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u32 bmr; /* 0xC4 TC Block Mode Register */
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} at91_tc_t;
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#define AT91_TC_BMR_TC0XC0S_TCLK0 0x00000000
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#define AT91_TC_BMR_TC0XC0S_NONE 0x00000001
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#define AT91_TC_BMR_TC0XC0S_TIOA1 0x00000002
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#define AT91_TC_BMR_TC0XC0S_TIOA2 0x00000003
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#define AT91_TC_BMR_TC1XC1S_TCLK1 0x00000000
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#define AT91_TC_BMR_TC1XC1S_NONE 0x00000004
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#define AT91_TC_BMR_TC1XC1S_TIOA0 0x00000008
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#define AT91_TC_BMR_TC1XC1S_TIOA2 0x0000000C
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#define AT91_TC_BMR_TC2XC2S_TCLK2 0x00000000
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#define AT91_TC_BMR_TC2XC2S_NONE 0x00000010
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#define AT91_TC_BMR_TC2XC2S_TIOA0 0x00000020
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#define AT91_TC_BMR_TC2XC2S_TIOA1 0x00000030
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#endif
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