/*
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* Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef AT91_MC_H
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#define AT91_MC_H
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#define AT91_ASM_MC_EBI_CSA (ATMEL_BASE_MC + 0x60)
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#define AT91_ASM_MC_EBI_CFG (ATMEL_BASE_MC + 0x64)
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#define AT91_ASM_MC_SMC_CSR0 (ATMEL_BASE_MC + 0x70)
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#define AT91_ASM_MC_SDRAMC_MR (ATMEL_BASE_MC + 0x90)
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#define AT91_ASM_MC_SDRAMC_TR (ATMEL_BASE_MC + 0x94)
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#define AT91_ASM_MC_SDRAMC_CR (ATMEL_BASE_MC + 0x98)
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#ifndef __ASSEMBLY__
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typedef struct at91_ebi {
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u32 csa; /* 0x00 Chip Select Assignment Register */
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u32 cfgr; /* 0x04 Configuration Register */
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u32 reserved[2];
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} at91_ebi_t;
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#define AT91_EBI_CSA_CS0A 0x0001
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#define AT91_EBI_CSA_CS1A 0x0002
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#define AT91_EBI_CSA_CS3A 0x0008
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#define AT91_EBI_CSA_CS4A 0x0010
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typedef struct at91_sdramc {
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u32 mr; /* 0x00 SDRAMC Mode Register */
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u32 tr; /* 0x04 SDRAMC Refresh Timer Register */
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u32 cr; /* 0x08 SDRAMC Configuration Register */
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u32 ssr; /* 0x0C SDRAMC Self Refresh Register */
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u32 lpr; /* 0x10 SDRAMC Low Power Register */
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u32 ier; /* 0x14 SDRAMC Interrupt Enable Register */
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u32 idr; /* 0x18 SDRAMC Interrupt Disable Register */
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u32 imr; /* 0x1C SDRAMC Interrupt Mask Register */
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u32 icr; /* 0x20 SDRAMC Interrupt Status Register */
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u32 reserved[3];
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} at91_sdramc_t;
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typedef struct at91_smc {
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u32 csr[8]; /* 0x00 SDRAMC Mode Register */
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} at91_smc_t;
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#define AT91_SMC_CSR_RWHOLD(x) ((x & 0x7) << 28)
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#define AT91_SMC_CSR_RWSETUP(x) ((x & 0x7) << 24)
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#define AT91_SMC_CSR_ACSS_STANDARD 0x00000000
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#define AT91_SMC_CSR_ACSS_1CYCLE 0x00010000
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#define AT91_SMC_CSR_ACSS_2CYCLE 0x00020000
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#define AT91_SMC_CSR_ACSS_3CYCLE 0x00030000
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#define AT91_SMC_CSR_DRP 0x00008000
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#define AT91_SMC_CSR_DBW_8 0x00004000
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#define AT91_SMC_CSR_DBW_16 0x00002000
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#define AT91_SMC_CSR_BAT_8 0x00000000
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#define AT91_SMC_CSR_BAT_16 0x00001000
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#define AT91_SMC_CSR_TDF(x) ((x & 0xF) << 8)
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#define AT91_SMC_CSR_WSEN 0x00000080
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#define AT91_SMC_CSR_NWS(x) (x & 0x7F)
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typedef struct at91_bfc {
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u32 mr; /* 0x00 SDRAMC Mode Register */
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} at91_bfc_t;
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typedef struct at91_mc {
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u32 rcr; /* 0x00 MC Remap Control Register */
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u32 asr; /* 0x04 MC Abort Status Register */
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u32 aasr; /* 0x08 MC Abort Address Status Reg */
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u32 mpr; /* 0x0C MC Master Priority Register */
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u32 reserved1[20]; /* 0x10-0x5C */
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at91_ebi_t ebi; /* 0x60 - 0x6C EBI */
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at91_smc_t smc; /* 0x70 - 0x8C SMC User Interface */
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at91_sdramc_t sdramc; /* 0x90 - 0xBC SDRAMC User Interface */
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at91_bfc_t bfc; /* 0xC0 BFC User Interface */
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u32 reserved2[15];
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} at91_mc_t;
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#endif
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#endif
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