/*
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* (C) Copyright 2016
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* Michael Kurz, michi.kurz@gmail.com.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _STM32_SYSCFG_H
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#define _STM32_SYSCFG_H
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struct stm32_syscfg_regs {
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u32 memrmp;
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u32 pmc;
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u32 exticr1;
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u32 exticr2;
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u32 exticr3;
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u32 exticr4;
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u32 cmpcr;
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};
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/*
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* SYSCFG registers base
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*/
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#define STM32_SYSCFG ((struct stm32_syscfg_regs *)STM32_SYSCFG_BASE)
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/* SYSCFG memory remap register */
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#define SYSCFG_MEMRMP_MEM_BOOT BIT(0)
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#define SYSCFG_MEMRMP_SWP_FMC BIT(10)
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/* SYSCFG peripheral mode configuration register */
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#define SYSCFG_PMC_ADCXDC2 BIT(16)
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#define SYSCFG_PMC_MII_RMII_SEL BIT(23)
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/* Compensation cell control register */
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#define SYSCFG_CMPCR_CMP_PD BIT(0)
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#define SYSCFG_CMPCR_READY BIT(8)
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#endif
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