/*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __REGS_UART_H__
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#define __REGS_UART_H__
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#define FFUART_BASE 0x40100000
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#define BTUART_BASE 0x40200000
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#define STUART_BASE 0x40700000
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#define HWUART_BASE 0x41600000
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struct pxa_uart_regs {
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union {
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uint32_t thr;
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uint32_t rbr;
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uint32_t dll;
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};
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union {
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uint32_t ier;
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uint32_t dlh;
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};
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union {
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uint32_t fcr;
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uint32_t iir;
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};
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uint32_t lcr;
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uint32_t mcr;
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uint32_t lsr;
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uint32_t msr;
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uint32_t spr;
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uint32_t isr;
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};
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#define IER_DMAE (1 << 7)
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#define IER_UUE (1 << 6)
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#define IER_NRZE (1 << 5)
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#define IER_RTIOE (1 << 4)
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#define IER_MIE (1 << 3)
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#define IER_RLSE (1 << 2)
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#define IER_TIE (1 << 1)
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#define IER_RAVIE (1 << 0)
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#define IIR_FIFOES1 (1 << 7)
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#define IIR_FIFOES0 (1 << 6)
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#define IIR_TOD (1 << 3)
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#define IIR_IID2 (1 << 2)
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#define IIR_IID1 (1 << 1)
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#define IIR_IP (1 << 0)
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#define FCR_ITL2 (1 << 7)
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#define FCR_ITL1 (1 << 6)
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#define FCR_RESETTF (1 << 2)
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#define FCR_RESETRF (1 << 1)
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#define FCR_TRFIFOE (1 << 0)
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#define FCR_ITL_1 0
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#define FCR_ITL_8 (FCR_ITL1)
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#define FCR_ITL_16 (FCR_ITL2)
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#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
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#define LCR_DLAB (1 << 7)
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#define LCR_SB (1 << 6)
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#define LCR_STKYP (1 << 5)
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#define LCR_EPS (1 << 4)
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#define LCR_PEN (1 << 3)
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#define LCR_STB (1 << 2)
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#define LCR_WLS1 (1 << 1)
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#define LCR_WLS0 (1 << 0)
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#define LSR_FIFOE (1 << 7)
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#define LSR_TEMT (1 << 6)
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#define LSR_TDRQ (1 << 5)
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#define LSR_BI (1 << 4)
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#define LSR_FE (1 << 3)
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#define LSR_PE (1 << 2)
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#define LSR_OE (1 << 1)
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#define LSR_DR (1 << 0)
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#define MCR_LOOP (1 << 4)
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#define MCR_OUT2 (1 << 3)
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#define MCR_OUT1 (1 << 2)
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#define MCR_RTS (1 << 1)
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#define MCR_DTR (1 << 0)
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#define MSR_DCD (1 << 7)
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#define MSR_RI (1 << 6)
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#define MSR_DSR (1 << 5)
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#define MSR_CTS (1 << 4)
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#define MSR_DDCD (1 << 3)
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#define MSR_TERI (1 << 2)
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#define MSR_DDSR (1 << 1)
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#define MSR_DCTS (1 << 0)
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#endif /* __REGS_UART_H__ */
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