/*
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* Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
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*
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* Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
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* Copyright (C) 2009 Nuvoton PS Team
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*
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* Special thanks to Nuvoton for providing hardware, spec sheets and
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* sample code upon which portions of this driver are based. Indirect
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* thanks also to Maxim Levitsky, whose ene_ir driver this driver is
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* modeled after.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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#include <linux/spinlock.h>
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#include <linux/ioctl.h>
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/* platform driver name to register */
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#define NVT_DRIVER_NAME "nuvoton-cir"
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/* debugging module parameter */
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static int debug;
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#define nvt_dbg(text, ...) \
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if (debug) \
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printk(KERN_DEBUG \
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KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
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#define nvt_dbg_verbose(text, ...) \
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if (debug > 1) \
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printk(KERN_DEBUG \
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KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
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#define nvt_dbg_wake(text, ...) \
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if (debug > 2) \
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printk(KERN_DEBUG \
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KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
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#define RX_BUF_LEN 32
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#define SIO_ID_MASK 0xfff0
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enum nvt_chip_ver {
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NVT_UNKNOWN = 0,
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NVT_W83667HG = 0xa510,
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NVT_6775F = 0xb470,
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NVT_6776F = 0xc330,
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NVT_6779D = 0xc560,
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NVT_INVALID = 0xffff,
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};
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struct nvt_chip {
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const char *name;
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enum nvt_chip_ver chip_ver;
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};
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struct nvt_dev {
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struct rc_dev *rdev;
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spinlock_t lock;
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/* for rx */
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u8 buf[RX_BUF_LEN];
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unsigned int pkts;
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/* EFER Config register index/data pair */
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u32 cr_efir;
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u32 cr_efdr;
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/* hardware I/O settings */
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unsigned long cir_addr;
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unsigned long cir_wake_addr;
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int cir_irq;
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enum nvt_chip_ver chip_ver;
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/* hardware id */
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u8 chip_major;
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u8 chip_minor;
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/* carrier period = 1 / frequency */
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u32 carrier;
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};
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/* buffer packet constants */
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#define BUF_PULSE_BIT 0x80
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#define BUF_LEN_MASK 0x7f
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#define BUF_REPEAT_BYTE 0x70
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#define BUF_REPEAT_MASK 0xf0
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/* CIR settings */
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/* total length of CIR and CIR WAKE */
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#define CIR_IOREG_LENGTH 0x0f
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/* RX limit length, 8 high bits for SLCH, 8 low bits for SLCL */
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#define CIR_RX_LIMIT_COUNT (IR_DEFAULT_TIMEOUT / US_TO_NS(SAMPLE_PERIOD))
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/* CIR Regs */
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#define CIR_IRCON 0x00
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#define CIR_IRSTS 0x01
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#define CIR_IREN 0x02
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#define CIR_RXFCONT 0x03
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#define CIR_CP 0x04
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#define CIR_CC 0x05
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#define CIR_SLCH 0x06
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#define CIR_SLCL 0x07
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#define CIR_FIFOCON 0x08
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#define CIR_IRFIFOSTS 0x09
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#define CIR_SRXFIFO 0x0a
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#define CIR_TXFCONT 0x0b
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#define CIR_STXFIFO 0x0c
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#define CIR_FCCH 0x0d
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#define CIR_FCCL 0x0e
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#define CIR_IRFSM 0x0f
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/* CIR IRCON settings */
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#define CIR_IRCON_RECV 0x80
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#define CIR_IRCON_WIREN 0x40
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#define CIR_IRCON_TXEN 0x20
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#define CIR_IRCON_RXEN 0x10
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#define CIR_IRCON_WRXINV 0x08
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#define CIR_IRCON_RXINV 0x04
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#define CIR_IRCON_SAMPLE_PERIOD_SEL_1 0x00
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#define CIR_IRCON_SAMPLE_PERIOD_SEL_25 0x01
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#define CIR_IRCON_SAMPLE_PERIOD_SEL_50 0x02
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#define CIR_IRCON_SAMPLE_PERIOD_SEL_100 0x03
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/* FIXME: make this a runtime option */
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/* select sample period as 50us */
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#define CIR_IRCON_SAMPLE_PERIOD_SEL CIR_IRCON_SAMPLE_PERIOD_SEL_50
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/* CIR IRSTS settings */
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#define CIR_IRSTS_RDR 0x80
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#define CIR_IRSTS_RTR 0x40
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#define CIR_IRSTS_PE 0x20
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#define CIR_IRSTS_RFO 0x10
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#define CIR_IRSTS_TE 0x08
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#define CIR_IRSTS_TTR 0x04
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#define CIR_IRSTS_TFU 0x02
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#define CIR_IRSTS_GH 0x01
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/* CIR IREN settings */
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#define CIR_IREN_RDR 0x80
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#define CIR_IREN_RTR 0x40
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#define CIR_IREN_PE 0x20
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#define CIR_IREN_RFO 0x10
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#define CIR_IREN_TE 0x08
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#define CIR_IREN_TTR 0x04
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#define CIR_IREN_TFU 0x02
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#define CIR_IREN_GH 0x01
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/* CIR FIFOCON settings */
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#define CIR_FIFOCON_TXFIFOCLR 0x80
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#define CIR_FIFOCON_TX_TRIGGER_LEV_31 0x00
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#define CIR_FIFOCON_TX_TRIGGER_LEV_24 0x10
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#define CIR_FIFOCON_TX_TRIGGER_LEV_16 0x20
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#define CIR_FIFOCON_TX_TRIGGER_LEV_8 0x30
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/* FIXME: make this a runtime option */
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/* select TX trigger level as 16 */
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#define CIR_FIFOCON_TX_TRIGGER_LEV CIR_FIFOCON_TX_TRIGGER_LEV_16
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#define CIR_FIFOCON_RXFIFOCLR 0x08
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#define CIR_FIFOCON_RX_TRIGGER_LEV_1 0x00
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#define CIR_FIFOCON_RX_TRIGGER_LEV_8 0x01
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#define CIR_FIFOCON_RX_TRIGGER_LEV_16 0x02
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#define CIR_FIFOCON_RX_TRIGGER_LEV_24 0x03
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/* FIXME: make this a runtime option */
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/* select RX trigger level as 24 */
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#define CIR_FIFOCON_RX_TRIGGER_LEV CIR_FIFOCON_RX_TRIGGER_LEV_24
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/* CIR IRFIFOSTS settings */
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#define CIR_IRFIFOSTS_IR_PENDING 0x80
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#define CIR_IRFIFOSTS_RX_GS 0x40
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#define CIR_IRFIFOSTS_RX_FTA 0x20
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#define CIR_IRFIFOSTS_RX_EMPTY 0x10
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#define CIR_IRFIFOSTS_RX_FULL 0x08
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#define CIR_IRFIFOSTS_TX_FTA 0x04
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#define CIR_IRFIFOSTS_TX_EMPTY 0x02
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#define CIR_IRFIFOSTS_TX_FULL 0x01
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/* CIR WAKE UP Regs */
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#define CIR_WAKE_IRCON 0x00
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#define CIR_WAKE_IRSTS 0x01
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#define CIR_WAKE_IREN 0x02
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#define CIR_WAKE_FIFO_CMP_DEEP 0x03
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#define CIR_WAKE_FIFO_CMP_TOL 0x04
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#define CIR_WAKE_FIFO_COUNT 0x05
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#define CIR_WAKE_SLCH 0x06
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#define CIR_WAKE_SLCL 0x07
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#define CIR_WAKE_FIFOCON 0x08
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#define CIR_WAKE_SRXFSTS 0x09
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#define CIR_WAKE_SAMPLE_RX_FIFO 0x0a
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#define CIR_WAKE_WR_FIFO_DATA 0x0b
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#define CIR_WAKE_RD_FIFO_ONLY 0x0c
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#define CIR_WAKE_RD_FIFO_ONLY_IDX 0x0d
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#define CIR_WAKE_FIFO_IGNORE 0x0e
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#define CIR_WAKE_IRFSM 0x0f
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/* CIR WAKE UP IRCON settings */
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#define CIR_WAKE_IRCON_DEC_RST 0x80
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#define CIR_WAKE_IRCON_MODE1 0x40
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#define CIR_WAKE_IRCON_MODE0 0x20
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#define CIR_WAKE_IRCON_RXEN 0x10
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#define CIR_WAKE_IRCON_R 0x08
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#define CIR_WAKE_IRCON_RXINV 0x04
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/* FIXME/jarod: make this a runtime option */
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/* select a same sample period like cir register */
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#define CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL CIR_IRCON_SAMPLE_PERIOD_SEL_50
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/* CIR WAKE IRSTS Bits */
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#define CIR_WAKE_IRSTS_RDR 0x80
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#define CIR_WAKE_IRSTS_RTR 0x40
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#define CIR_WAKE_IRSTS_PE 0x20
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#define CIR_WAKE_IRSTS_RFO 0x10
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#define CIR_WAKE_IRSTS_GH 0x08
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#define CIR_WAKE_IRSTS_IR_PENDING 0x01
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/* CIR WAKE UP IREN Bits */
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#define CIR_WAKE_IREN_RDR 0x80
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#define CIR_WAKE_IREN_RTR 0x40
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#define CIR_WAKE_IREN_PE 0x20
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#define CIR_WAKE_IREN_RFO 0x10
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#define CIR_WAKE_IREN_GH 0x08
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/* CIR WAKE FIFOCON settings */
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#define CIR_WAKE_FIFOCON_RXFIFOCLR 0x08
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#define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_67 0x00
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#define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_66 0x01
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#define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_65 0x02
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#define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_64 0x03
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/* FIXME: make this a runtime option */
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/* select WAKE UP RX trigger level as 67 */
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#define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_67
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/* CIR WAKE SRXFSTS settings */
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#define CIR_WAKE_IRFIFOSTS_RX_GS 0x80
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#define CIR_WAKE_IRFIFOSTS_RX_FTA 0x40
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#define CIR_WAKE_IRFIFOSTS_RX_EMPTY 0x20
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#define CIR_WAKE_IRFIFOSTS_RX_FULL 0x10
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/*
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* The CIR Wake FIFO buffer is 67 bytes long, but the stock remote wakes
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* the system comparing only 65 bytes (fails with this set to 67)
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*/
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#define CIR_WAKE_FIFO_CMP_BYTES 65
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/* CIR Wake byte comparison tolerance */
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#define CIR_WAKE_CMP_TOLERANCE 5
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/*
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* Extended Function Enable Registers:
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* Extended Function Index Register
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* Extended Function Data Register
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*/
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#define CR_EFIR 0x2e
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#define CR_EFDR 0x2f
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/* Possible alternate EFER values, depends on how the chip is wired */
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#define CR_EFIR2 0x4e
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#define CR_EFDR2 0x4f
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/* Extended Function Mode enable/disable magic values */
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#define EFER_EFM_ENABLE 0x87
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#define EFER_EFM_DISABLE 0xaa
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/* Config regs we need to care about */
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#define CR_SOFTWARE_RESET 0x02
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#define CR_LOGICAL_DEV_SEL 0x07
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#define CR_CHIP_ID_HI 0x20
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#define CR_CHIP_ID_LO 0x21
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#define CR_DEV_POWER_DOWN 0x22 /* bit 2 is CIR power, default power on */
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#define CR_OUTPUT_PIN_SEL 0x27
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#define CR_MULTIFUNC_PIN_SEL 0x2c
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#define CR_LOGICAL_DEV_EN 0x30 /* valid for all logical devices */
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/* next three regs valid for both the CIR and CIR_WAKE logical devices */
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#define CR_CIR_BASE_ADDR_HI 0x60
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#define CR_CIR_BASE_ADDR_LO 0x61
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#define CR_CIR_IRQ_RSRC 0x70
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/* next three regs valid only for ACPI logical dev */
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#define CR_ACPI_CIR_WAKE 0xe0
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#define CR_ACPI_IRQ_EVENTS 0xf6
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#define CR_ACPI_IRQ_EVENTS2 0xf7
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/* Logical devices that we need to care about */
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#define LOGICAL_DEV_LPT 0x01
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#define LOGICAL_DEV_CIR 0x06
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#define LOGICAL_DEV_ACPI 0x0a
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#define LOGICAL_DEV_CIR_WAKE 0x0e
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#define LOGICAL_DEV_DISABLE 0x00
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#define LOGICAL_DEV_ENABLE 0x01
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#define CIR_WAKE_ENABLE_BIT 0x08
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#define PME_INTR_CIR_PASS_BIT 0x08
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/* w83677hg CIR pin config */
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#define OUTPUT_PIN_SEL_MASK 0xbc
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#define OUTPUT_ENABLE_CIR 0x01 /* Pin95=CIRRX, Pin96=CIRTX1 */
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#define OUTPUT_ENABLE_CIRWB 0x40 /* enable wide-band sensor */
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/* w83667hg CIR pin config */
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#define MULTIFUNC_PIN_SEL_MASK 0x1f
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#define MULTIFUNC_ENABLE_CIR 0x80 /* Pin75=CIRRX, Pin76=CIRTX1 */
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#define MULTIFUNC_ENABLE_CIRWB 0x20 /* enable wide-band sensor */
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/* MCE CIR signal length, related on sample period */
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/* MCE CIR controller signal length: about 43ms
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* 43ms / 50us (sample period) * 0.85 (inaccuracy)
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*/
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#define CONTROLLER_BUF_LEN_MIN 830
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/* MCE CIR keyboard signal length: about 26ms
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* 26ms / 50us (sample period) * 0.85 (inaccuracy)
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*/
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#define KEYBOARD_BUF_LEN_MAX 650
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#define KEYBOARD_BUF_LEN_MIN 610
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/* MCE CIR mouse signal length: about 24ms
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* 24ms / 50us (sample period) * 0.85 (inaccuracy)
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*/
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#define MOUSE_BUF_LEN_MIN 565
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#define CIR_SAMPLE_PERIOD 50
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#define CIR_SAMPLE_LOW_INACCURACY 0.85
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/* MAX silence time that driver will sent to lirc */
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#define MAX_SILENCE_TIME 60000
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#if CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_100
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#define SAMPLE_PERIOD 100
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#elif CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_50
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#define SAMPLE_PERIOD 50
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#elif CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_25
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#define SAMPLE_PERIOD 25
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#else
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#define SAMPLE_PERIOD 1
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#endif
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/* as VISTA MCE definition, valid carrier value */
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#define MAX_CARRIER 60000
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#define MIN_CARRIER 30000
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/* max wakeup sequence length */
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#define WAKEUP_MAX_SIZE 65
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