/*
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*************************************************************************
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* Rockchip driver for CIF ISP 1.0
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* (Based on Intel driver for sofiaxxx)
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*
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* Copyright (C) 2015 Intel Mobile Communications GmbH
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* Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*************************************************************************
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*/
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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#include <linux/clk.h>
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#include <linux/reset.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/platform_data/rk_isp10_platform.h>
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#define VI_IRCL 0x0014
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#define MRV_MIPI_BASE 0x1C00
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#define MRV_MIPI_CTRL 0x00
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/*
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* GRF_IO_VSEL
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*/
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#define GRF_IO_VSEL_OFFSET (0x0900)
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#define DVP_V18SEL ((1 << 1) | (1 << 17))
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#define DVP_V33SEL ((0 << 1) | (1 << 17))
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/*
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* GRF_IO_VSEL
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*/
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#define GRF_GPIO2B_E_OFFSET (0x0204)
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#define CIF_CLKOUT_STRENGTH(a) \
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((((a) & 0x03) << 3) | (0x03 << 19))
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#define GRF_SOC_STATUS1 (0x0e2a4)
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#define GRF_SOC_CON9_OFFSET (0x6224)
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#define DPHY_RX0_TURNREQUEST_MASK (0xF << 16)
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#define DPHY_RX0_TURNREQUEST_BIT (0)
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#define GRF_SOC_CON21_OFFSET (0x6254)
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#define DPHY_RX0_FORCERXMODE_MASK (0xF << 20)
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#define DPHY_RX0_FORCERXMODE_BIT (4)
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#define DPHY_RX0_FORCETXSTOPMODE_MASK (0xF << 24)
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#define DPHY_RX0_FORCETXSTOPMODE_BIT (8)
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#define DPHY_RX0_TURNDISABLE_MASK (0xF << 28)
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#define DPHY_RX0_TURNDISABLE_BIT (12)
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#define DPHY_RX0_ENABLE_MASK (0xF << 16)
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#define DPHY_RX0_ENABLE_BIT (0)
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#define GRF_SOC_CON23_OFFSET (0x625c)
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#define DPHY_TX1RX1_TURNDISABLE_MASK (0xF << 28)
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#define DPHY_TX1RX1_TURNDISABLE_BIT (12)
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#define DPHY_TX1RX1_FORCERXMODE_MASK (0xF << 20)
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#define DPHY_TX1RX1_FORCERXMODE_BIT (4)
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#define DPHY_TX1RX1_FORCETXSTOPMODE_MASK (0xF << 24)
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#define DPHY_TX1RX1_FORCETXSTOPMODE_BIT (8)
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#define DPHY_TX1RX1_ENABLE_MASK (0xF << 16)
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#define DPHY_TX1RX1_ENABLE_BIT (0)
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#define GRF_SOC_CON24_OFFSET (0x6260)
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#define DPHY_TX1RX1_MASTERSLAVEZ_MASK (0x1 << 23)
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#define DPHY_TX1RX1_MASTERSLAVEZ_BIT (7)
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#define DPHY_TX1RX1_BASEDIR_MASK (0x1 << 21)
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#define DPHY_TX1RX1_BASEDIR_BIT (5)
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#define DPHY_RX1_MASK (0x1 << 20)
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#define DPHY_RX1_SEL_BIT (4)
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#define GRF_SOC_CON25_OFFSET (0x6264)
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#define DPHY_RX0_TESTCLK_MASK (0x1 << 25)
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#define DPHY_RX0_TESTCLK_BIT (9)
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#define DPHY_RX0_TESTCLR_MASK (0x1 << 26)
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#define DPHY_RX0_TESTCLR_BIT (10)
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#define DPHY_RX0_TESTDIN_MASK (0xFF << 16)
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#define DPHY_RX0_TESTDIN_BIT (0)
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#define DPHY_RX0_TESTEN_MASK (0x1 << 24)
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#define DPHY_RX0_TESTEN_BIT (8)
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#define DPHY_TX1RX1_TURNREQUEST_MASK (0xF << 16)
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#define DPHY_TX1RX1_TURNREQUEST_BIT (0)
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#define DSIHOST_PHY_SHUTDOWNZ (0x00a0)
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#define DSIHOST_DPHY_RSTZ (0x00a0)
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#define DSIHOST_PHY_TEST_CTRL0 (0x00b4)
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#define DSIHOST_PHY_TEST_CTRL1 (0x00b8)
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#define write_cifisp_reg(addr, val) \
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__raw_writel(val, (addr) + isp_cfg->isp_base)
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#define read_cifisp_reg(addr) \
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__raw_readl((addr) + isp_cfg->isp_base)
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#define write_grf_reg(addr, val) \
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regmap_write(isp_cfg->regmap_grf, addr, val)
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#define read_grf_reg(addr, val) \
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regmap_read(isp_cfg->regmap_grf, addr, val)
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#define write_dsihost_reg(addr, val) \
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__raw_writel(val, (addr) + isp_cfg->dsihost_base)
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#define read_dsihost_reg(addr) \
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__raw_readl((addr) + isp_cfg->dsihost_base)
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enum cif_isp10_isp_idx {
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CIF_ISP10_ISP0 = 0,
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CIF_ISP10_ISP1 = 1
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};
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struct cif_isp10_clk_rst_rk3399 {
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struct clk *hclk_isp0_noc;
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struct clk *hclk_isp0_wrapper;
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struct clk *hclk_isp1_noc;
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struct clk *hclk_isp1_wrapper;
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struct clk *aclk_isp0_noc;
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struct clk *aclk_isp0_wrapper;
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struct clk *aclk_isp1_noc;
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struct clk *aclk_isp1_wrapper;
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struct clk *clk_isp0;
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struct clk *clk_isp1;
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struct clk *pclkin_isp1;
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struct clk *pclk_dphy_ref;
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struct clk *pclk_dphytxrx;
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struct clk *pclk_dphyrx;
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struct clk *cif_clk_out;
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struct clk *cif_clk_pll;
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struct clk *cif_clk_mipi_dsi;
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struct clk *cif_clk_mipi_dphy_cfg;
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};
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struct cif_isp10_rk3399 {
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struct regmap *regmap_grf;
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void __iomem *dsihost_base;
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void __iomem *isp_base;
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struct cif_isp10_clk_rst_rk3399 clk_rst;
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struct cif_isp10_device *cif_isp10;
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enum cif_isp10_isp_idx isp_idx;
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};
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struct mipi_dphy_hsfreqrange {
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unsigned int range_l;
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unsigned int range_h;
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unsigned char cfg_bit;
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};
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static struct mipi_dphy_hsfreqrange mipi_dphy_hsfreq_range[] = {
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{80, 90, 0x00},
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{90, 100, 0x10},
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{100, 110, 0x20},
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{110, 130, 0x01},
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{130, 140, 0x11},
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{140, 150, 0x21},
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{150, 170, 0x02},
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{170, 180, 0x12},
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{180, 200, 0x22},
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{200, 220, 0x03},
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{220, 240, 0x13},
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{240, 250, 0x23},
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{250, 270, 0x4},
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{270, 300, 0x14},
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{300, 330, 0x5},
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{330, 360, 0x15},
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{360, 400, 0x25},
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{400, 450, 0x06},
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{450, 500, 0x16},
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{500, 550, 0x07},
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{550, 600, 0x17},
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{600, 650, 0x08},
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{650, 700, 0x18},
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{700, 750, 0x09},
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{750, 800, 0x19},
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{800, 850, 0x29},
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{850, 900, 0x39},
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{900, 950, 0x0a},
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{950, 1000, 0x1a},
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{1000, 1050, 0x2a},
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{1100, 1150, 0x3a},
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{1150, 1200, 0x0b},
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{1200, 1250, 0x1b},
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{1250, 1300, 0x2b},
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{1300, 1350, 0x0c},
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{1350, 1400, 0x1c},
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{1400, 1450, 0x2c},
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{1450, 1500, 0x3c}
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};
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static int mipi_dphy0_wr_reg(struct cif_isp10_rk3399 *isp_cfg, unsigned char addr, unsigned char data)
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{
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/*
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* TESTCLK=1
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* TESTEN =1,TESTDIN=addr
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* TESTCLK=0
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*/
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write_grf_reg(GRF_SOC_CON25_OFFSET,
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DPHY_RX0_TESTCLK_MASK | (1 << DPHY_RX0_TESTCLK_BIT));
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write_grf_reg(GRF_SOC_CON25_OFFSET,
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((addr << DPHY_RX0_TESTDIN_BIT) | DPHY_RX0_TESTDIN_MASK
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| (1 << DPHY_RX0_TESTEN_BIT) | DPHY_RX0_TESTEN_MASK));
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write_grf_reg(GRF_SOC_CON25_OFFSET, DPHY_RX0_TESTCLK_MASK);
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/*
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* write data:
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* TESTEN =0,TESTDIN=data
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* TESTCLK=1
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*/
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if (data != 0xff) {
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write_grf_reg(GRF_SOC_CON25_OFFSET,
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((data << DPHY_RX0_TESTDIN_BIT) |
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DPHY_RX0_TESTDIN_MASK | DPHY_RX0_TESTEN_MASK));
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write_grf_reg(GRF_SOC_CON25_OFFSET,
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DPHY_RX0_TESTCLK_MASK | (1 << DPHY_RX0_TESTCLK_BIT));
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}
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return 0;
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}
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static int mipi_dphy0_rd_reg(struct cif_isp10_rk3399 *isp_cfg, unsigned char addr)
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{
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int val = 0;
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/*TESTCLK=1*/
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write_grf_reg(GRF_SOC_CON25_OFFSET, DPHY_RX0_TESTCLK_MASK |
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(1 << DPHY_RX0_TESTCLK_BIT));
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/*TESTEN =1,TESTDIN=addr*/
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write_grf_reg(GRF_SOC_CON25_OFFSET,
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((addr << DPHY_RX0_TESTDIN_BIT) |
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DPHY_RX0_TESTDIN_MASK |
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(1 << DPHY_RX0_TESTEN_BIT) |
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DPHY_RX0_TESTEN_MASK));
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/*TESTCLK=0*/
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write_grf_reg(GRF_SOC_CON25_OFFSET, DPHY_RX0_TESTCLK_MASK);
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read_grf_reg(GRF_SOC_STATUS1, &val);
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return val & 0xff;
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}
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static int mipi_dphy1_wr_reg(struct cif_isp10_rk3399 *isp_cfg, unsigned char addr, unsigned char data)
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{
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/*
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* TESTEN =1,TESTDIN=addr
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* TESTCLK=0
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* TESTEN =0,TESTDIN=data
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* TESTCLK=1
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*/
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write_dsihost_reg(DSIHOST_PHY_TEST_CTRL1, (0x00010000 | addr));
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write_dsihost_reg(DSIHOST_PHY_TEST_CTRL0, 0x00000000);
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write_dsihost_reg(DSIHOST_PHY_TEST_CTRL1, (0x00000000 | data));
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write_dsihost_reg(DSIHOST_PHY_TEST_CTRL0, 0x00000002);
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return 0;
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}
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static int mipi_dphy1_rd_reg(struct cif_isp10_rk3399 *isp_cfg, unsigned char addr)
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{
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/* TESTEN =1,TESTDIN=addr */
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write_dsihost_reg(DSIHOST_PHY_TEST_CTRL1, (0x00010000 | addr));
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/* TESTCLK=0 */
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write_dsihost_reg(DSIHOST_PHY_TEST_CTRL0, 0x00000000);
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return ((read_dsihost_reg(DSIHOST_PHY_TEST_CTRL1) & 0xff00) >> 8);
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}
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static int mipi_dphy_cfg(struct cif_isp10_rk3399 *isp_cfg, struct pltfrm_cam_mipi_config *para)
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{
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unsigned char hsfreqrange = 0xff, i;
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struct mipi_dphy_hsfreqrange *hsfreqrange_p;
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unsigned char datalane_en, input_sel;
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hsfreqrange_p = mipi_dphy_hsfreq_range;
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for (i = 0;
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i < (sizeof(mipi_dphy_hsfreq_range) /
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sizeof(struct mipi_dphy_hsfreqrange));
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i++) {
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if ((para->bit_rate > hsfreqrange_p->range_l) &&
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(para->bit_rate <= hsfreqrange_p->range_h)) {
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hsfreqrange = hsfreqrange_p->cfg_bit;
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break;
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}
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hsfreqrange_p++;
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}
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if (hsfreqrange == 0xff)
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hsfreqrange = 0x00;
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hsfreqrange <<= 1;
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input_sel = para->dphy_index;
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datalane_en = 0;
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for (i = 0; i < para->nb_lanes; i++)
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datalane_en |= (1 << i);
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if (input_sel == 0) {
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/*
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* According to the sequence of RK3399_TXRX_DPHY, the setting of isp0 mipi
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* will affect txrx dphy in default state of grf_soc_con24.
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*/
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write_grf_reg(GRF_SOC_CON24_OFFSET,
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DPHY_TX1RX1_MASTERSLAVEZ_MASK |
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(0x0 << DPHY_TX1RX1_MASTERSLAVEZ_BIT) |
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DPHY_TX1RX1_BASEDIR_MASK |
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(0x1 << DPHY_TX1RX1_BASEDIR_BIT) |
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DPHY_RX1_MASK | 0x0 << DPHY_RX1_SEL_BIT);
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write_grf_reg(GRF_SOC_CON21_OFFSET,
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DPHY_RX0_FORCERXMODE_MASK |
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(0x0 << DPHY_RX0_FORCERXMODE_BIT) |
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DPHY_RX0_FORCETXSTOPMODE_MASK |
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(0x0 << DPHY_RX0_FORCETXSTOPMODE_BIT));
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/* set lane num */
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write_grf_reg(GRF_SOC_CON21_OFFSET,
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DPHY_RX0_ENABLE_MASK |
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(datalane_en << DPHY_RX0_ENABLE_BIT));
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/* set lan turndisab as 1 */
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write_grf_reg(GRF_SOC_CON21_OFFSET,
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DPHY_RX0_TURNDISABLE_MASK |
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(0xf << DPHY_RX0_TURNDISABLE_BIT));
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write_grf_reg(GRF_SOC_CON21_OFFSET, (0x0 << 4) | (0xf << 20));
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/* set lan turnrequest as 0 */
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write_grf_reg(GRF_SOC_CON9_OFFSET,
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DPHY_RX0_TURNREQUEST_MASK |
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(0x0 << DPHY_RX0_TURNREQUEST_BIT));
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/* phy start */
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/*
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* TESTCLK=1
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* TESTCLR=1
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* delay 100us
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* TESTCLR=0
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*/
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write_grf_reg(GRF_SOC_CON25_OFFSET,
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DPHY_RX0_TESTCLK_MASK |
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(0x1 << DPHY_RX0_TESTCLK_BIT)); /* TESTCLK=1 */
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write_grf_reg(GRF_SOC_CON25_OFFSET,
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DPHY_RX0_TESTCLR_MASK |
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(0x1 << DPHY_RX0_TESTCLR_BIT)); /* TESTCLR=1 */
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usleep_range(100, 150);
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/* TESTCLR=0 zyc */
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write_grf_reg(GRF_SOC_CON25_OFFSET,
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DPHY_RX0_TESTCLR_MASK);
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usleep_range(100, 150);
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/* set clock lane */
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mipi_dphy0_wr_reg
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(isp_cfg, 0x34, 0);
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/* HS hsfreqrange & lane 0 settle bypass */
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mipi_dphy0_wr_reg(isp_cfg, 0x44, hsfreqrange);
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mipi_dphy0_wr_reg(isp_cfg, 0x54, 0);
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mipi_dphy0_wr_reg(isp_cfg, 0x84, 0);
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mipi_dphy0_wr_reg(isp_cfg, 0x94, 0);
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mipi_dphy0_wr_reg(isp_cfg, 0x75, 0x04);
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mipi_dphy0_rd_reg(isp_cfg, 0x75);
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/* Normal operation */
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/*
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* TESTCLK=1
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* TESTEN =0
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*/
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mipi_dphy0_wr_reg(isp_cfg, 0x0, -1);
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write_grf_reg(GRF_SOC_CON25_OFFSET,
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DPHY_RX0_TESTCLK_MASK | (1 << DPHY_RX0_TESTCLK_BIT));
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write_grf_reg(GRF_SOC_CON25_OFFSET,
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(DPHY_RX0_TESTEN_MASK));
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write_cifisp_reg((MRV_MIPI_BASE + MRV_MIPI_CTRL),
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read_cifisp_reg(MRV_MIPI_BASE + MRV_MIPI_CTRL)
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| (0x0f << 8));
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} else if (input_sel == 1) {
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write_grf_reg(GRF_SOC_CON23_OFFSET,
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DPHY_RX0_FORCERXMODE_MASK |
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(0x0 << DPHY_RX0_FORCERXMODE_BIT) |
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DPHY_RX0_FORCETXSTOPMODE_MASK |
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(0x0 << DPHY_RX0_FORCETXSTOPMODE_BIT));
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write_grf_reg(GRF_SOC_CON24_OFFSET,
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DPHY_TX1RX1_MASTERSLAVEZ_MASK |
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(0x0 << DPHY_TX1RX1_MASTERSLAVEZ_BIT) |
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DPHY_TX1RX1_BASEDIR_MASK |
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(0x1 << DPHY_TX1RX1_BASEDIR_BIT) |
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DPHY_RX1_MASK | 0x0 << DPHY_RX1_SEL_BIT);
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/* set lane num */
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write_grf_reg(GRF_SOC_CON23_OFFSET,
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DPHY_TX1RX1_ENABLE_MASK |
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(datalane_en << DPHY_TX1RX1_ENABLE_BIT));
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/* set lan turndisab as 1 */
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write_grf_reg(GRF_SOC_CON23_OFFSET,
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DPHY_TX1RX1_TURNDISABLE_MASK |
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(0xf << DPHY_TX1RX1_TURNDISABLE_BIT));
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write_grf_reg(GRF_SOC_CON23_OFFSET, (0x0 << 4) | (0xf << 20));
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/* set lan turnrequest as 0 */
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write_grf_reg(GRF_SOC_CON24_OFFSET,
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DPHY_TX1RX1_TURNREQUEST_MASK |
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(0x0 << DPHY_TX1RX1_TURNREQUEST_BIT));
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/* phy1 start */
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/*
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* SHUTDOWNZ=0
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* RSTZ=0
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* TESTCLK=1
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* TESTCLR=1 TESTCLK=1
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* TESTCLR=0 TESTCLK=1
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*/
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write_dsihost_reg(DSIHOST_PHY_SHUTDOWNZ, 0x00000000);
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write_dsihost_reg(DSIHOST_DPHY_RSTZ, 0x00000000);
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write_dsihost_reg(DSIHOST_PHY_TEST_CTRL0, 0x00000002);
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write_dsihost_reg(DSIHOST_PHY_TEST_CTRL1, 0x00000003);
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usleep_range(100, 150);
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write_dsihost_reg(DSIHOST_PHY_TEST_CTRL0, 0x00000002);
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usleep_range(100, 150);
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/* set clock lane */
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mipi_dphy1_wr_reg(isp_cfg, 0x34, 0x00);
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mipi_dphy1_wr_reg(isp_cfg, 0x44, hsfreqrange);
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mipi_dphy1_wr_reg(isp_cfg, 0x54, 0);
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mipi_dphy1_wr_reg(isp_cfg, 0x84, 0);
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mipi_dphy1_wr_reg(isp_cfg, 0x94, 0);
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mipi_dphy1_wr_reg(isp_cfg, 0x75, 0x04);
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mipi_dphy1_rd_reg(isp_cfg, 0x0);
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/*
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* TESTCLK=1
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* TESTEN =0
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* SHUTDOWNZ=1
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* RSTZ=1
|
*/
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write_dsihost_reg(DSIHOST_PHY_TEST_CTRL0, 0x00000002);
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write_dsihost_reg(DSIHOST_PHY_TEST_CTRL1, 0x00000000);
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/*SHUTDOWNZ=1, RSTZ=1*/
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write_dsihost_reg(DSIHOST_DPHY_RSTZ, 0x00000003);
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write_cifisp_reg((MRV_MIPI_BASE + MRV_MIPI_CTRL),
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read_cifisp_reg(MRV_MIPI_BASE + MRV_MIPI_CTRL)
|
| (0x0f << 8));
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} else {
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goto fail;
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}
|
|
return 0;
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fail:
|
return -1;
|
}
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|
static int soc_clk_enable(struct cif_isp10_rk3399 *isp_cfg)
|
{
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struct cif_isp10_clk_rst_rk3399 *clk_rst = &isp_cfg->clk_rst;
|
|
if (isp_cfg->isp_idx == CIF_ISP10_ISP0) {
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clk_prepare_enable(clk_rst->hclk_isp0_noc);
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clk_prepare_enable(clk_rst->hclk_isp0_wrapper);
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clk_prepare_enable(clk_rst->aclk_isp0_noc);
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clk_prepare_enable(clk_rst->aclk_isp0_wrapper);
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clk_prepare_enable(clk_rst->clk_isp0);
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clk_prepare_enable(clk_rst->pclk_dphyrx);
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clk_prepare_enable(clk_rst->cif_clk_out);
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clk_prepare_enable(clk_rst->pclk_dphy_ref);
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} else {
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clk_prepare_enable(clk_rst->hclk_isp1_noc);
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clk_prepare_enable(clk_rst->hclk_isp1_wrapper);
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clk_prepare_enable(clk_rst->aclk_isp1_noc);
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clk_prepare_enable(clk_rst->aclk_isp1_wrapper);
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clk_prepare_enable(clk_rst->clk_isp1);
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clk_prepare_enable(clk_rst->pclkin_isp1);
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clk_prepare_enable(clk_rst->pclk_dphytxrx);
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clk_prepare_enable(clk_rst->cif_clk_mipi_dsi);
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clk_prepare_enable(clk_rst->cif_clk_mipi_dphy_cfg);
|
clk_prepare_enable(clk_rst->cif_clk_out);
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clk_prepare_enable(clk_rst->pclk_dphy_ref);
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}
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|
return 0;
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}
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|
static int soc_clk_disable(struct cif_isp10_rk3399 *isp_cfg)
|
{
|
struct cif_isp10_clk_rst_rk3399 *clk_rst = &isp_cfg->clk_rst;
|
|
if (isp_cfg->isp_idx == CIF_ISP10_ISP0) {
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clk_disable_unprepare(clk_rst->hclk_isp0_noc);
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clk_disable_unprepare(clk_rst->hclk_isp0_wrapper);
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clk_disable_unprepare(clk_rst->aclk_isp0_noc);
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clk_disable_unprepare(clk_rst->aclk_isp0_wrapper);
|
clk_disable_unprepare(clk_rst->clk_isp0);
|
clk_disable_unprepare(clk_rst->pclk_dphyrx);
|
if (!IS_ERR_OR_NULL(clk_rst->cif_clk_pll))
|
clk_set_parent(clk_rst->cif_clk_out,
|
clk_rst->cif_clk_pll);
|
clk_disable_unprepare(clk_rst->cif_clk_out);
|
clk_disable_unprepare(clk_rst->pclk_dphy_ref);
|
} else {
|
clk_disable_unprepare(clk_rst->hclk_isp1_noc);
|
clk_disable_unprepare(clk_rst->hclk_isp1_wrapper);
|
clk_disable_unprepare(clk_rst->aclk_isp1_noc);
|
clk_disable_unprepare(clk_rst->aclk_isp1_wrapper);
|
clk_disable_unprepare(clk_rst->clk_isp1);
|
clk_disable_unprepare(clk_rst->pclkin_isp1);
|
clk_disable_unprepare(clk_rst->pclk_dphytxrx);
|
clk_disable_unprepare(clk_rst->cif_clk_mipi_dsi);
|
clk_disable_unprepare(clk_rst->cif_clk_mipi_dphy_cfg);
|
if (!IS_ERR_OR_NULL(clk_rst->cif_clk_pll))
|
clk_set_parent(clk_rst->cif_clk_out,
|
clk_rst->cif_clk_pll);
|
clk_disable_unprepare(clk_rst->cif_clk_out);
|
clk_disable_unprepare(clk_rst->pclk_dphy_ref);
|
}
|
|
return 0;
|
}
|
|
static int soc_init(struct cif_isp10_rk3399 **isp_cfg, struct pltfrm_soc_init_para *init)
|
{
|
struct cif_isp10_clk_rst_rk3399 *clk_rst;
|
struct platform_device *pdev = init->pdev;
|
struct device_node *np = pdev->dev.of_node, *node;
|
struct resource *res;
|
struct cif_isp10_rk3399 *isp_cfg_tmp;
|
int err;
|
|
*isp_cfg = NULL;
|
|
isp_cfg_tmp = (struct cif_isp10_rk3399 *)devm_kzalloc(
|
&pdev->dev,
|
sizeof(struct cif_isp10_rk3399),
|
GFP_KERNEL);
|
if (!isp_cfg_tmp) {
|
dev_err(&pdev->dev, "Can't allocate cif_isp10_rk3399\n");
|
err = -ENOMEM;
|
goto alloc_failed;
|
}
|
|
node = of_parse_phandle(np, "rockchip,grf", 0);
|
if (node) {
|
isp_cfg_tmp->regmap_grf = syscon_node_to_regmap(node);
|
if (IS_ERR(isp_cfg_tmp->regmap_grf)) {
|
dev_err(&pdev->dev, "Can't allocate cif_isp10_rk3399\n");
|
err = -ENODEV;
|
goto regmap_failed;
|
}
|
}
|
|
clk_rst = &isp_cfg_tmp->clk_rst;
|
|
if (strcmp(pdev->name, "ff910000.cif_isp") == 0) {
|
clk_rst->hclk_isp0_noc =
|
devm_clk_get(&pdev->dev, "hclk_isp0_noc");
|
clk_rst->hclk_isp0_wrapper =
|
devm_clk_get(&pdev->dev, "hclk_isp0_wrapper");
|
clk_rst->aclk_isp0_noc =
|
devm_clk_get(&pdev->dev, "aclk_isp0_noc");
|
clk_rst->aclk_isp0_wrapper =
|
devm_clk_get(&pdev->dev, "aclk_isp0_wrapper");
|
clk_rst->clk_isp0 =
|
devm_clk_get(&pdev->dev, "clk_isp0");
|
clk_rst->pclk_dphyrx =
|
devm_clk_get(&pdev->dev, "pclk_dphyrx");
|
clk_rst->cif_clk_out =
|
devm_clk_get(&pdev->dev, "clk_cif_out");
|
clk_rst->cif_clk_pll =
|
devm_clk_get(&pdev->dev, "clk_cif_pll");
|
clk_rst->pclk_dphy_ref =
|
devm_clk_get(&pdev->dev, "pclk_dphy_ref");
|
|
if (IS_ERR_OR_NULL(clk_rst->hclk_isp0_noc) ||
|
IS_ERR_OR_NULL(clk_rst->hclk_isp0_wrapper) ||
|
IS_ERR_OR_NULL(clk_rst->aclk_isp0_noc) ||
|
IS_ERR_OR_NULL(clk_rst->aclk_isp0_wrapper) ||
|
IS_ERR_OR_NULL(clk_rst->clk_isp0) ||
|
IS_ERR_OR_NULL(clk_rst->pclk_dphyrx) ||
|
IS_ERR_OR_NULL(clk_rst->cif_clk_out) ||
|
IS_ERR_OR_NULL(clk_rst->pclk_dphy_ref)) {
|
dev_err(&pdev->dev, "Get rk3399 cif isp10 clock resouce failed !\n");
|
err = -EINVAL;
|
goto clk_failed;
|
}
|
|
clk_set_rate(clk_rst->clk_isp0, 420000000);
|
isp_cfg_tmp->isp_idx = CIF_ISP10_ISP0;
|
} else {
|
res = platform_get_resource_byname(pdev,
|
IORESOURCE_MEM, "dsihost-register");
|
if (!res) {
|
dev_err(&pdev->dev,
|
"platform_get_resource_byname dsihost-register failed\n");
|
err = -ENODEV;
|
goto regmap_failed;
|
}
|
isp_cfg_tmp->dsihost_base = devm_ioremap_resource(&pdev->dev, res);
|
if (IS_ERR_OR_NULL(isp_cfg_tmp->dsihost_base)) {
|
dev_err(&pdev->dev, "devm_ioremap_resource failed\n");
|
if (IS_ERR(isp_cfg_tmp->dsihost_base))
|
err = PTR_ERR(isp_cfg_tmp->dsihost_base);
|
else
|
err = -ENODEV;
|
goto regmap_failed;
|
}
|
|
clk_rst->hclk_isp1_noc =
|
devm_clk_get(&pdev->dev, "hclk_isp1_noc");
|
clk_rst->hclk_isp1_wrapper =
|
devm_clk_get(&pdev->dev, "hclk_isp1_wrapper");
|
clk_rst->aclk_isp1_noc =
|
devm_clk_get(&pdev->dev, "aclk_isp1_noc");
|
clk_rst->aclk_isp1_wrapper =
|
devm_clk_get(&pdev->dev, "aclk_isp1_wrapper");
|
clk_rst->clk_isp1 =
|
devm_clk_get(&pdev->dev, "clk_isp1");
|
clk_rst->pclkin_isp1 =
|
devm_clk_get(&pdev->dev, "pclkin_isp1");
|
clk_rst->pclk_dphytxrx =
|
devm_clk_get(&pdev->dev, "pclk_dphytxrx");
|
|
clk_rst->cif_clk_mipi_dsi =
|
devm_clk_get(&pdev->dev, "pclk_mipi_dsi");
|
clk_rst->cif_clk_mipi_dphy_cfg =
|
devm_clk_get(&pdev->dev, "mipi_dphy_cfg");
|
|
clk_rst->cif_clk_out =
|
devm_clk_get(&pdev->dev, "clk_cif_out");
|
clk_rst->cif_clk_pll =
|
devm_clk_get(&pdev->dev, "clk_cif_pll");
|
clk_rst->pclk_dphy_ref =
|
devm_clk_get(&pdev->dev, "pclk_dphy_ref");
|
|
if (IS_ERR_OR_NULL(clk_rst->hclk_isp1_noc) ||
|
IS_ERR_OR_NULL(clk_rst->hclk_isp1_wrapper) ||
|
IS_ERR_OR_NULL(clk_rst->aclk_isp1_noc) ||
|
IS_ERR_OR_NULL(clk_rst->aclk_isp1_wrapper) ||
|
IS_ERR_OR_NULL(clk_rst->clk_isp1) ||
|
IS_ERR_OR_NULL(clk_rst->pclkin_isp1) ||
|
IS_ERR_OR_NULL(clk_rst->pclk_dphytxrx) ||
|
IS_ERR_OR_NULL(clk_rst->cif_clk_mipi_dsi) ||
|
IS_ERR_OR_NULL(clk_rst->cif_clk_mipi_dphy_cfg) ||
|
IS_ERR_OR_NULL(clk_rst->cif_clk_out) ||
|
IS_ERR_OR_NULL(clk_rst->pclk_dphy_ref)) {
|
dev_err(&pdev->dev, "Get rk3399 cif isp10 clock resouce failed !\n");
|
err = -EINVAL;
|
goto clk_failed;
|
}
|
|
clk_set_rate(clk_rst->clk_isp1, 420000000);
|
isp_cfg_tmp->isp_idx = CIF_ISP10_ISP1;
|
}
|
|
isp_cfg_tmp->isp_base = init->isp_base;
|
*isp_cfg = isp_cfg_tmp;
|
|
return 0;
|
|
clk_failed:
|
if (!IS_ERR_OR_NULL(clk_rst->hclk_isp0_noc))
|
devm_clk_put(&pdev->dev, clk_rst->hclk_isp0_noc);
|
|
if (!IS_ERR_OR_NULL(clk_rst->hclk_isp0_wrapper))
|
devm_clk_put(&pdev->dev, clk_rst->hclk_isp0_wrapper);
|
|
if (!IS_ERR_OR_NULL(clk_rst->aclk_isp0_noc))
|
devm_clk_put(&pdev->dev, clk_rst->aclk_isp0_noc);
|
|
if (!IS_ERR_OR_NULL(clk_rst->aclk_isp0_wrapper))
|
devm_clk_put(&pdev->dev, clk_rst->aclk_isp0_wrapper);
|
|
if (!IS_ERR_OR_NULL(clk_rst->clk_isp0))
|
devm_clk_put(&pdev->dev, clk_rst->clk_isp0);
|
|
if (!IS_ERR_OR_NULL(clk_rst->pclk_dphyrx))
|
devm_clk_put(&pdev->dev, clk_rst->pclk_dphyrx);
|
|
if (!IS_ERR_OR_NULL(clk_rst->hclk_isp1_noc))
|
devm_clk_put(&pdev->dev, clk_rst->hclk_isp1_noc);
|
|
if (!IS_ERR_OR_NULL(clk_rst->hclk_isp1_wrapper))
|
devm_clk_put(&pdev->dev, clk_rst->hclk_isp1_wrapper);
|
|
if (!IS_ERR_OR_NULL(clk_rst->aclk_isp1_noc))
|
devm_clk_put(&pdev->dev, clk_rst->aclk_isp1_noc);
|
|
if (!IS_ERR_OR_NULL(clk_rst->aclk_isp1_wrapper))
|
devm_clk_put(&pdev->dev, clk_rst->aclk_isp1_wrapper);
|
|
if (!IS_ERR_OR_NULL(clk_rst->clk_isp1))
|
devm_clk_put(&pdev->dev, clk_rst->clk_isp1);
|
|
if (!IS_ERR_OR_NULL(clk_rst->pclkin_isp1))
|
devm_clk_put(&pdev->dev, clk_rst->pclkin_isp1);
|
|
if (!IS_ERR_OR_NULL(clk_rst->pclk_dphytxrx))
|
devm_clk_put(&pdev->dev, clk_rst->pclk_dphytxrx);
|
|
if (!IS_ERR_OR_NULL(clk_rst->cif_clk_mipi_dsi))
|
devm_clk_put(&pdev->dev, clk_rst->cif_clk_mipi_dsi);
|
|
if (!IS_ERR_OR_NULL(clk_rst->cif_clk_mipi_dphy_cfg))
|
devm_clk_put(&pdev->dev, clk_rst->cif_clk_mipi_dphy_cfg);
|
|
if (!IS_ERR_OR_NULL(clk_rst->cif_clk_out))
|
devm_clk_put(&pdev->dev, clk_rst->cif_clk_out);
|
|
if (!IS_ERR_OR_NULL(clk_rst->pclk_dphy_ref))
|
devm_clk_put(&pdev->dev, clk_rst->pclk_dphy_ref);
|
|
regmap_failed:
|
|
alloc_failed:
|
|
return err;
|
}
|
|
int pltfrm_rk3399_cfg(struct pltfrm_soc_cfg_para *cfg)
|
{
|
int ret = -1;
|
struct cif_isp10_rk3399 *isp_cfg = NULL;
|
|
if (cfg->isp_config == NULL) {
|
return -1;
|
} else {
|
isp_cfg = (struct cif_isp10_rk3399 *)(*cfg->isp_config);
|
if (isp_cfg == NULL && cfg->cmd != PLTFRM_SOC_INIT)
|
return -1;
|
}
|
|
switch (cfg->cmd) {
|
case PLTFRM_MCLK_CFG: {
|
struct pltfrm_soc_mclk_para *mclk_para;
|
|
mclk_para = (struct pltfrm_soc_mclk_para *)cfg->cfg_para;
|
if (mclk_para->io_voltage == PLTFRM_IO_1V8)
|
write_grf_reg(GRF_IO_VSEL_OFFSET, DVP_V18SEL);
|
else
|
write_grf_reg(GRF_IO_VSEL_OFFSET, DVP_V33SEL);
|
|
write_grf_reg(GRF_GPIO2B_E_OFFSET,
|
CIF_CLKOUT_STRENGTH(mclk_para->drv_strength));
|
ret = 0;
|
break;
|
}
|
case PLTFRM_MIPI_DPHY_CFG:
|
ret = mipi_dphy_cfg(isp_cfg, (struct pltfrm_cam_mipi_config *)cfg->cfg_para);
|
break;
|
|
case PLTFRM_CLKEN:
|
ret = soc_clk_enable(isp_cfg);
|
break;
|
|
case PLTFRM_CLKDIS:
|
ret = soc_clk_disable(isp_cfg);
|
break;
|
|
case PLTFRM_CLKRST:
|
write_cifisp_reg(VI_IRCL, 0xf7f);
|
usleep_range(10, 15);
|
write_cifisp_reg(VI_IRCL, 0x00);
|
ret = 0;
|
break;
|
|
case PLTFRM_SOC_INIT:
|
ret = soc_init((struct cif_isp10_rk3399 **)cfg->isp_config, (struct pltfrm_soc_init_para *)cfg->cfg_para);
|
break;
|
|
default:
|
break;
|
}
|
|
return ret;
|
}
|
