/*
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*************************************************************************
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* Rockchip driver for CIF ISP 1.0
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* (Based on Intel driver for sofiaxxx)
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*
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* Copyright (C) 2015 Intel Mobile Communications GmbH
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* Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*************************************************************************
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*/
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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#include <linux/clk.h>
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#include <linux/reset.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/platform_data/rk_isp10_platform.h>
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#define ONE_LANE_ENABLE_BIT 0x1
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#define TWO_LANE_ENABLE_BIT 0x2
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#define FOUR_LANE_ENABLE_BIT 0x4
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#define MRV_MIPI_BASE 0x1C00
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#define MRV_MIPI_CTRL 0x00
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/*
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* GRF_SOC_CON14
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* bit 0 dphy_rx0_testclr
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* bit 1 dphy_rx0_testclk
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* bit 2 dphy_rx0_testen
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* bit 3:10 dphy_rx0_testdin
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*/
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#define GRF_SOC_CON14_OFFSET (0x027c)
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#define DPHY_RX0_TESTCLR_MASK (0x1 << 16)
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#define DPHY_RX0_TESTCLK_MASK (0x1 << 17)
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#define DPHY_RX0_TESTEN_MASK (0x1 << 18)
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#define DPHY_RX0_TESTDIN_MASK (0xff << 19)
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#define DPHY_RX0_TESTCLR BIT(0)
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#define DPHY_RX0_TESTCLK BIT(1)
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#define DPHY_RX0_TESTEN BIT(2)
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#define DPHY_RX0_TESTDIN_OFFSET (3)
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#define DPHY_TX1RX1_ENABLECLK_MASK (0x1 << 28)
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#define DPHY_RX1_SRC_SEL_MASK (0x1 << 29)
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#define DPHY_TX1RX1_MASTERSLAVEZ_MASK (0x1 << 30)
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#define DPHY_TX1RX1_BASEDIR_OFFSET (0x1 << 31)
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#define DPHY_TX1RX1_ENABLECLK (0x1 << 12)
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#define DPHY_TX1RX1_DISABLECLK (0x0 << 12)
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#define DPHY_RX1_SRC_SEL_ISP (0x1 << 13)
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#define DPHY_TX1RX1_SLAVEZ (0x0 << 14)
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#define DPHY_TX1RX1_BASEDIR_REC (0x1 << 15)
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/*
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* GRF_SOC_CON6
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* bit 0 grf_con_disable_isp
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* bit 1 grf_con_isp_dphy_sel 1'b0 mipi phy rx0
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*/
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#define GRF_SOC_CON6_OFFSET (0x025c)
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#define MIPI_PHY_DISABLE_ISP_MASK (0x1 << 16)
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#define MIPI_PHY_DISABLE_ISP (0x0 << 0)
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#define DSI_CSI_TESTBUS_SEL_MASK (0x1 << 30)
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#define DSI_CSI_TESTBUS_SEL_OFFSET_BIT (14)
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#define MIPI_PHY_DPHYSEL_OFFSET_MASK (0x1 << 17)
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#define MIPI_PHY_DPHYSEL_OFFSET_BIT (0x1)
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/*
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* GRF_SOC_CON10
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* bit12:15 grf_dphy_rx0_enable
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* bit 0:3 turn disable
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*/
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#define GRF_SOC_CON10_OFFSET (0x026c)
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#define DPHY_RX0_TURN_DISABLE_MASK (0xf << 16)
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#define DPHY_RX0_TURN_DISABLE_OFFSET_BITS (0x0)
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#define DPHY_RX0_ENABLE_MASK (0xf << 28)
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#define DPHY_RX0_ENABLE_OFFSET_BITS (12)
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/*
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* GRF_SOC_CON9
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* bit12:15 grf_dphy_rx0_enable
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* bit 0:3 turn disable
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*/
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#define GRF_SOC_CON9_OFFSET (0x0268)
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#define DPHY_TX1RX1_TURN_DISABLE_MASK (0xf << 16)
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#define DPHY_TX1RX1_TURN_DISABLE_OFFSET_BITS (0x0)
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#define DPHY_TX1RX1_ENABLE_MASK (0xf << 28)
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#define DPHY_TX1RX1_ENABLE_OFFSET_BITS (12)
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/*
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* GRF_SOC_CON15
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* bit 0:3 turn request
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*/
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#define GRF_SOC_CON15_OFFSET (0x03a4)
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#define DPHY_RX0_TURN_REQUEST_MASK (0xf << 16)
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#define DPHY_RX0_TURN_REQUEST_OFFSET_BITS (0x0)
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#define DPHY_TX1RX1_TURN_REQUEST_MASK (0xf << 20)
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#define DPHY_TX1RX1_TURN_REQUEST_OFFSET_BITS (0x0)
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/*
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* GRF_SOC_STATUS21
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* bit0:7 dphy_rx0_testdout
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*/
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#define GRF_SOC_STATUS21_OFFSET (0x2D4)
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#define DPHY_RX0_TESTDOUT(a) ((a) & 0xff)
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/*
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* GRF_IO_VSEL
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*/
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#define GRF_IO_VSEL_OFFSET (0x0380)
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#define DVP_V18SEL ((1 << 1) | (1 << 17))
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#define DVP_V33SEL ((0 << 1) | (1 << 17))
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/*
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* GRF_IO_VSEL
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*/
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#define GRF_GPIO2B_E_OFFSET (0x0380)
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#define CIF_CLKOUT_STRENGTH(a) ((((a) & 0x03) << 3) | (0x03 << 19))
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/*
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* CSI HOST
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*/
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#define CSIHOST_PHY_TEST_CTRL0 (0x30)
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#define CSIHOST_PHY_TEST_CTRL1 (0x34)
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#define CSIHOST_PHY_SHUTDOWNZ (0x08)
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#define CSIHOST_DPHY_RSTZ (0x0c)
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#define CSIHOST_N_LANES (0x04)
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#define CSIHOST_CSI2_RESETN (0x10)
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#define CSIHOST_PHY_STATE (0x14)
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#define CSIHOST_DATA_IDS1 (0x18)
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#define CSIHOST_DATA_IDS2 (0x1C)
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#define CSIHOST_ERR1 (0x20)
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#define CSIHOST_ERR2 (0x24)
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#define write_cifisp_reg(addr, val) \
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__raw_writel(val, (addr) + rk3288->isp_base)
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#define read_cifisp_reg(addr) \
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__raw_readl((addr) + rk3288->isp_base)
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#define write_grf_reg(addr, val) \
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regmap_write(rk3288->regmap_grf, addr, val)
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#define read_grf_reg(addr, val) regmap_read(rk3288->regmap_grf, addr, val)
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#define write_csihost_reg(addr, val) \
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__raw_writel(val, (addr) + rk3288->csihost_base)
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#define read_csihost_reg(addr) __raw_readl((addr) + rk3288->csihost_base)
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struct cif_isp10_clk_rst_rk3288 {
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struct clk *aclk_isp;
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struct clk *hclk_isp;
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struct clk *sclk_isp;
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struct clk *sclk_isp_jpe;
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struct clk *sclk_mipidsi_24m;
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struct clk *pclk_mipi_csi;
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struct clk *pclk_isp_in;
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struct reset_control *isp_rst;
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};
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struct cif_isp10_rk3288 {
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struct regmap *regmap_grf;
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void __iomem *csihost_base;
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void __iomem *isp_base;
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struct cif_isp10_clk_rst_rk3288 clk_rst;
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struct cif_isp10_device *cif_isp10;
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};
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struct mipi_dphy_hsfreqrange {
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unsigned int range_l;
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unsigned int range_h;
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unsigned char cfg_bit;
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};
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static struct mipi_dphy_hsfreqrange mipi_dphy_hsfreq_range[] = {
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{80, 90, 0x00},
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{90, 100, 0x10},
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{100, 110, 0x20},
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{110, 130, 0x01},
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{130, 140, 0x11},
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{140, 150, 0x21},
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{150, 170, 0x02},
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{170, 180, 0x12},
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{180, 200, 0x22},
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{200, 220, 0x03},
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{220, 240, 0x13},
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{240, 250, 0x23},
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{250, 270, 0x4},
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{270, 300, 0x14},
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{300, 330, 0x5},
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{330, 360, 0x15},
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{360, 400, 0x25},
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{400, 450, 0x06},
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{450, 500, 0x16},
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{500, 550, 0x07},
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{550, 600, 0x17},
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{600, 650, 0x08},
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{650, 700, 0x18},
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{700, 750, 0x09},
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{750, 800, 0x19},
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{800, 850, 0x29},
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{850, 900, 0x39},
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{900, 950, 0x0a},
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{950, 1000, 0x1a}
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};
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static struct cif_isp10_rk3288 *rk3288;
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static int mipi_dphy0_wr_reg(unsigned char addr, unsigned char data)
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{
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/*
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* TESTCLK=1
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* TESTEN =1,TESTDIN=addr
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* TESTCLK=0
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*/
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write_grf_reg(GRF_SOC_CON14_OFFSET,
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DPHY_RX0_TESTCLK_MASK | DPHY_RX0_TESTCLK);
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write_grf_reg(GRF_SOC_CON14_OFFSET,
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((addr << DPHY_RX0_TESTDIN_OFFSET) | DPHY_RX0_TESTDIN_MASK
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| DPHY_RX0_TESTEN | DPHY_RX0_TESTEN_MASK));
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write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLK_MASK);
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/*
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* write data:
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* TESTEN =0,TESTDIN=data
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* TESTCLK=1
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*/
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if (data != 0xff) {
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write_grf_reg(GRF_SOC_CON14_OFFSET,
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((data << DPHY_RX0_TESTDIN_OFFSET) |
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DPHY_RX0_TESTDIN_MASK | DPHY_RX0_TESTEN_MASK));
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write_grf_reg(GRF_SOC_CON14_OFFSET,
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DPHY_RX0_TESTCLK_MASK | DPHY_RX0_TESTCLK);
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}
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return 0;
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}
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static int mipi_dphy1_wr_reg(unsigned char addr, unsigned char data)
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{
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/*
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* TESTEN =1,TESTDIN=addr
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* TESTCLK=0
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* TESTEN =0,TESTDIN=data
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* TESTCLK=1
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*/
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write_csihost_reg(CSIHOST_PHY_TEST_CTRL1, (0x00010000 | addr));
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write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000000);
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write_csihost_reg(CSIHOST_PHY_TEST_CTRL1, (0x00000000 | data));
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write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000002);
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return 0;
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}
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static int mipi_dphy1_rd_reg(unsigned char addr)
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{
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return (read_csihost_reg(((CSIHOST_PHY_TEST_CTRL1) & 0xff00)) >> 8);
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}
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static int mipi_dphy_cfg(struct pltfrm_cam_mipi_config *para)
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{
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unsigned char hsfreqrange = 0xff, i;
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struct mipi_dphy_hsfreqrange *hsfreqrange_p;
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unsigned char datalane_en, input_sel;
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hsfreqrange_p = mipi_dphy_hsfreq_range;
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for (i = 0;
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i < (sizeof(mipi_dphy_hsfreq_range) /
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sizeof(struct mipi_dphy_hsfreqrange));
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i++) {
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if ((para->bit_rate > hsfreqrange_p->range_l) &&
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(para->bit_rate <= hsfreqrange_p->range_h)) {
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hsfreqrange = hsfreqrange_p->cfg_bit;
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break;
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}
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hsfreqrange_p++;
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}
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if (hsfreqrange == 0xff)
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hsfreqrange = 0x00;
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hsfreqrange <<= 1;
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input_sel = para->dphy_index;
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datalane_en = 0;
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for (i = 0; i < para->nb_lanes; i++)
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datalane_en |= (1 << i);
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if (input_sel == 0) {
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write_grf_reg(GRF_SOC_CON6_OFFSET,
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MIPI_PHY_DPHYSEL_OFFSET_MASK |
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(input_sel << MIPI_PHY_DPHYSEL_OFFSET_BIT));
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/* set lane num */
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write_grf_reg(GRF_SOC_CON10_OFFSET,
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DPHY_RX0_ENABLE_MASK |
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(datalane_en << DPHY_RX0_ENABLE_OFFSET_BITS));
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/* set lan turndisab as 1 */
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write_grf_reg(GRF_SOC_CON10_OFFSET,
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DPHY_RX0_TURN_DISABLE_MASK |
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(0xf << DPHY_RX0_TURN_DISABLE_OFFSET_BITS));
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write_grf_reg(GRF_SOC_CON10_OFFSET,
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(0x0 << 4) | (0xf << 20));
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/* set lan turnrequest as 0 */
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write_grf_reg(GRF_SOC_CON15_OFFSET,
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DPHY_RX0_TURN_REQUEST_MASK |
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(0x0 << DPHY_RX0_TURN_REQUEST_OFFSET_BITS));
|
|
/* phy start */
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/*
|
* TESTCLK=1
|
* TESTCLR=1
|
* delay 100us
|
* TESTCLR=0
|
*/
|
write_grf_reg(GRF_SOC_CON14_OFFSET,
|
DPHY_RX0_TESTCLK_MASK | DPHY_RX0_TESTCLK);
|
write_grf_reg(GRF_SOC_CON14_OFFSET,
|
DPHY_RX0_TESTCLR_MASK | DPHY_RX0_TESTCLR);
|
usleep_range(100, 150);
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write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLR_MASK);
|
usleep_range(100, 150);
|
|
/* set clock lane */
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mipi_dphy0_wr_reg(0x34, 0x15);
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if (datalane_en == ONE_LANE_ENABLE_BIT) {
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mipi_dphy0_wr_reg(0x44, hsfreqrange);
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} else if (datalane_en == TWO_LANE_ENABLE_BIT) {
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mipi_dphy0_wr_reg(0x44, hsfreqrange);
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mipi_dphy0_wr_reg(0x54, hsfreqrange);
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} else if (datalane_en == FOUR_LANE_ENABLE_BIT) {
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mipi_dphy0_wr_reg(0x44, hsfreqrange);
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mipi_dphy0_wr_reg(0x54, hsfreqrange);
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mipi_dphy0_wr_reg(0x84, hsfreqrange);
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mipi_dphy0_wr_reg(0x94, hsfreqrange);
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}
|
|
/* Normal operation */
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/*
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* TESTCLK=1
|
* TESTEN =0
|
*/
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mipi_dphy0_wr_reg(0x0, -1);
|
write_grf_reg(GRF_SOC_CON14_OFFSET,
|
DPHY_RX0_TESTCLK_MASK | DPHY_RX0_TESTCLK);
|
write_grf_reg(GRF_SOC_CON14_OFFSET,
|
(DPHY_RX0_TESTEN_MASK));
|
|
write_cifisp_reg((MRV_MIPI_BASE + MRV_MIPI_CTRL),
|
read_cifisp_reg(MRV_MIPI_BASE + MRV_MIPI_CTRL) |
|
(0x0f << 8));
|
|
} else if (input_sel == 1) {
|
write_grf_reg(GRF_SOC_CON6_OFFSET,
|
MIPI_PHY_DPHYSEL_OFFSET_MASK |
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(input_sel << MIPI_PHY_DPHYSEL_OFFSET_BIT));
|
write_grf_reg(GRF_SOC_CON6_OFFSET,
|
DSI_CSI_TESTBUS_SEL_MASK |
|
(1 << DSI_CSI_TESTBUS_SEL_OFFSET_BIT));
|
|
write_grf_reg(GRF_SOC_CON14_OFFSET,
|
DPHY_RX1_SRC_SEL_ISP | DPHY_RX1_SRC_SEL_MASK);
|
write_grf_reg(GRF_SOC_CON14_OFFSET,
|
DPHY_TX1RX1_SLAVEZ | DPHY_TX1RX1_MASTERSLAVEZ_MASK);
|
write_grf_reg(GRF_SOC_CON14_OFFSET,
|
DPHY_TX1RX1_BASEDIR_REC | DPHY_TX1RX1_BASEDIR_OFFSET);
|
|
/* set lane num */
|
write_grf_reg(GRF_SOC_CON9_OFFSET,
|
DPHY_TX1RX1_ENABLE_MASK |
|
(datalane_en << DPHY_TX1RX1_ENABLE_OFFSET_BITS));
|
/* set lan turndisab as 1 */
|
write_grf_reg(GRF_SOC_CON9_OFFSET,
|
DPHY_TX1RX1_TURN_DISABLE_MASK |
|
(0xf << DPHY_TX1RX1_TURN_DISABLE_OFFSET_BITS));
|
/* set lan turnrequest as 0 */
|
write_grf_reg(GRF_SOC_CON15_OFFSET,
|
DPHY_TX1RX1_TURN_REQUEST_MASK |
|
(0x0 << DPHY_TX1RX1_TURN_REQUEST_OFFSET_BITS));
|
|
/* phy1 start */
|
/*
|
* SHUTDOWNZ=0
|
* RSTZ=0
|
* TESTCLK=1
|
* TESTCLR=1 TESTCLK=1
|
* TESTCLR=0 TESTCLK=1
|
*/
|
write_csihost_reg(CSIHOST_PHY_SHUTDOWNZ, 0x00000000);
|
write_csihost_reg(CSIHOST_DPHY_RSTZ, 0x00000000);
|
write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000002);
|
write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000003);
|
usleep_range(100, 150);
|
write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000002);
|
usleep_range(100, 150);
|
|
/* set clock lane */
|
mipi_dphy1_wr_reg(0x34, 0x15);
|
|
if (datalane_en == ONE_LANE_ENABLE_BIT) {
|
mipi_dphy1_wr_reg(0x44, hsfreqrange);
|
} else if (datalane_en == TWO_LANE_ENABLE_BIT) {
|
mipi_dphy1_wr_reg(0x44, hsfreqrange);
|
mipi_dphy1_wr_reg(0x54, hsfreqrange);
|
} else if (datalane_en == FOUR_LANE_ENABLE_BIT) {
|
mipi_dphy1_wr_reg(0x44, hsfreqrange);
|
mipi_dphy1_wr_reg(0x54, hsfreqrange);
|
mipi_dphy1_wr_reg(0x84, hsfreqrange);
|
mipi_dphy1_wr_reg(0x94, hsfreqrange);
|
}
|
|
mipi_dphy1_rd_reg(0x0);
|
/*
|
* TESTCLK=1
|
* TESTEN =0
|
* SHUTDOWNZ=1
|
* RSTZ=1
|
*/
|
write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000002);
|
write_csihost_reg(CSIHOST_PHY_TEST_CTRL1, 0x00000000);
|
write_csihost_reg(CSIHOST_PHY_SHUTDOWNZ, 0x00000001);
|
write_csihost_reg(CSIHOST_DPHY_RSTZ, 0x00000001);
|
} else {
|
goto fail;
|
}
|
|
return 0;
|
fail:
|
return -1;
|
}
|
|
static int soc_clk_enable(void)
|
{
|
struct cif_isp10_clk_rst_rk3288 *clk_rst = &rk3288->clk_rst;
|
|
clk_prepare_enable(clk_rst->hclk_isp);
|
clk_prepare_enable(clk_rst->aclk_isp);
|
clk_prepare_enable(clk_rst->sclk_isp);
|
clk_prepare_enable(clk_rst->sclk_isp_jpe);
|
clk_prepare_enable(clk_rst->sclk_mipidsi_24m);
|
clk_prepare_enable(clk_rst->pclk_isp_in);
|
clk_prepare_enable(clk_rst->pclk_mipi_csi);
|
return 0;
|
}
|
|
static int soc_clk_disable(void)
|
{
|
struct cif_isp10_clk_rst_rk3288 *clk_rst = &rk3288->clk_rst;
|
|
clk_disable_unprepare(clk_rst->hclk_isp);
|
clk_disable_unprepare(clk_rst->aclk_isp);
|
clk_disable_unprepare(clk_rst->sclk_isp);
|
clk_disable_unprepare(clk_rst->sclk_isp_jpe);
|
clk_disable_unprepare(clk_rst->sclk_mipidsi_24m);
|
clk_disable_unprepare(clk_rst->pclk_isp_in);
|
clk_disable_unprepare(clk_rst->pclk_mipi_csi);
|
return 0;
|
}
|
|
static int soc_init(struct pltfrm_soc_init_para *init)
|
{
|
struct cif_isp10_clk_rst_rk3288 *clk_rst;
|
struct platform_device *pdev = init->pdev;
|
struct device_node *np = pdev->dev.of_node, *node;
|
struct resource *res;
|
int err;
|
|
rk3288 = (struct cif_isp10_rk3288 *)devm_kzalloc(
|
&pdev->dev,
|
sizeof(struct cif_isp10_rk3288),
|
GFP_KERNEL);
|
if (!rk3288) {
|
dev_err(&pdev->dev, "Can't allocate cif_isp10_rk3288\n");
|
err = -ENOMEM;
|
goto alloc_failed;
|
}
|
|
node = of_parse_phandle(np, "rockchip,grf", 0);
|
if (node) {
|
rk3288->regmap_grf = syscon_node_to_regmap(node);
|
if (IS_ERR(rk3288->regmap_grf)) {
|
dev_err(&pdev->dev, "Can't allocate cif_isp10_rk3288\n");
|
err = -ENODEV;
|
goto regmap_failed;
|
}
|
}
|
|
res = platform_get_resource_byname(pdev,
|
IORESOURCE_MEM, "csihost-register");
|
if (!res) {
|
dev_err(&pdev->dev,
|
"platform_get_resource_byname csihost-register failed\n");
|
err = -ENODEV;
|
goto regmap_failed;
|
}
|
rk3288->csihost_base = devm_ioremap_resource(&pdev->dev, res);
|
if (IS_ERR_OR_NULL(rk3288->csihost_base)) {
|
dev_err(&pdev->dev, "devm_ioremap_resource failed\n");
|
if (IS_ERR(rk3288->csihost_base))
|
err = PTR_ERR(rk3288->csihost_base);
|
else
|
err = -ENODEV;
|
goto regmap_failed;
|
}
|
|
clk_rst = &rk3288->clk_rst;
|
clk_rst->aclk_isp = devm_clk_get(&pdev->dev, "aclk_isp");
|
clk_rst->hclk_isp = devm_clk_get(&pdev->dev, "hclk_isp");
|
clk_rst->sclk_isp = devm_clk_get(&pdev->dev, "sclk_isp");
|
clk_rst->sclk_isp_jpe = devm_clk_get(&pdev->dev, "sclk_isp_jpe");
|
clk_rst->sclk_mipidsi_24m =
|
devm_clk_get(&pdev->dev, "sclk_mipidsi_24m");
|
clk_rst->pclk_mipi_csi = devm_clk_get(&pdev->dev, "pclk_mipi_csi");
|
clk_rst->isp_rst = devm_reset_control_get(&pdev->dev, "rst_isp");
|
clk_rst->pclk_isp_in = devm_clk_get(&pdev->dev, "pclk_isp_in");
|
|
if (IS_ERR_OR_NULL(clk_rst->aclk_isp) ||
|
IS_ERR_OR_NULL(clk_rst->hclk_isp) ||
|
IS_ERR_OR_NULL(clk_rst->sclk_isp) ||
|
IS_ERR_OR_NULL(clk_rst->sclk_isp_jpe) ||
|
IS_ERR_OR_NULL(clk_rst->pclk_mipi_csi) ||
|
IS_ERR_OR_NULL(clk_rst->isp_rst) ||
|
IS_ERR_OR_NULL(clk_rst->pclk_isp_in) ||
|
IS_ERR_OR_NULL(clk_rst->sclk_mipidsi_24m)) {
|
dev_err(&pdev->dev, "Get rk3288 cif isp10 clock resouce failed !\n");
|
err = -EINVAL;
|
goto clk_failed;
|
}
|
|
clk_set_rate(clk_rst->sclk_isp, 400000000);
|
clk_set_rate(clk_rst->sclk_isp_jpe, 400000000);
|
reset_control_deassert(clk_rst->isp_rst);
|
|
rk3288->isp_base = init->isp_base;
|
return 0;
|
|
clk_failed:
|
if (!IS_ERR_OR_NULL(clk_rst->aclk_isp))
|
devm_clk_put(&pdev->dev, clk_rst->aclk_isp);
|
if (!IS_ERR_OR_NULL(clk_rst->hclk_isp))
|
devm_clk_put(&pdev->dev, clk_rst->hclk_isp);
|
if (!IS_ERR_OR_NULL(clk_rst->sclk_isp))
|
devm_clk_put(&pdev->dev, clk_rst->sclk_isp);
|
if (!IS_ERR_OR_NULL(clk_rst->sclk_isp_jpe))
|
devm_clk_put(&pdev->dev, clk_rst->sclk_isp_jpe);
|
if (!IS_ERR_OR_NULL(clk_rst->pclk_mipi_csi))
|
devm_clk_put(&pdev->dev, clk_rst->pclk_mipi_csi);
|
if (!IS_ERR_OR_NULL(clk_rst->pclk_isp_in))
|
devm_clk_put(&pdev->dev, clk_rst->pclk_isp_in);
|
if (!IS_ERR_OR_NULL(clk_rst->sclk_mipidsi_24m))
|
devm_clk_put(&pdev->dev, clk_rst->sclk_mipidsi_24m);
|
|
if (!IS_ERR_OR_NULL(clk_rst->isp_rst))
|
reset_control_put(clk_rst->isp_rst);
|
|
regmap_failed:
|
|
alloc_failed:
|
|
return err;
|
}
|
|
int pltfrm_rk3288_cfg(struct pltfrm_soc_cfg_para *cfg)
|
{
|
switch (cfg->cmd) {
|
case PLTFRM_MCLK_CFG: {
|
struct pltfrm_soc_mclk_para *mclk_para;
|
|
mclk_para = (struct pltfrm_soc_mclk_para *)cfg->cfg_para;
|
if (mclk_para->io_voltage == PLTFRM_IO_1V8)
|
write_grf_reg(GRF_IO_VSEL_OFFSET, DVP_V18SEL);
|
else
|
write_grf_reg(GRF_IO_VSEL_OFFSET, DVP_V33SEL);
|
|
write_grf_reg(GRF_GPIO2B_E_OFFSET,
|
CIF_CLKOUT_STRENGTH(mclk_para->drv_strength));
|
break;
|
}
|
case PLTFRM_MIPI_DPHY_CFG:
|
mipi_dphy_cfg((struct pltfrm_cam_mipi_config *)cfg->cfg_para);
|
break;
|
|
case PLTFRM_CLKEN:
|
soc_clk_enable();
|
break;
|
|
case PLTFRM_CLKDIS:
|
soc_clk_disable();
|
break;
|
|
case PLTFRM_CLKRST:
|
reset_control_assert(rk3288->clk_rst.isp_rst);
|
usleep_range(10, 15);
|
reset_control_deassert(rk3288->clk_rst.isp_rst);
|
break;
|
|
case PLTFRM_SOC_INIT:
|
soc_init((struct pltfrm_soc_init_para *)cfg->cfg_para);
|
break;
|
|
default:
|
break;
|
}
|
|
return 0;
|
}
|
