/*
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*************************************************************************
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* Rockchip driver for CIF ISP 1.0
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* (Based on Intel driver for sofiaxxx)
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*
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* Copyright (C) 2015 Intel Mobile Communications GmbH
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* Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*************************************************************************
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*/
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#ifndef _CIF_ISP10_PLTFRM_H
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#define _CIF_ISP10_PLTFRM_H
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#include <linux/kernel.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/wait.h>
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#include <linux/string.h>
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#include <linux/platform_data/rk_isp10_platform.h>
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struct cif_isp10_strm_fmt;
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struct cif_isp10_csi_config;
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struct cif_isp10_device;
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struct cif_isp10_img_src;
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struct pltfrm_cam_itf;
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enum cif_isp10_pinctrl_state;
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enum cif_isp10_inp;
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enum cif_isp10_pm_state;
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#define CIF_ISP10_PLTFRM_DEVICE struct device *
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#define CIF_ISP10_PLTFRM_MEM_IO_ADDR void __iomem *
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#define CIF_ISP10_PLTFRM_EVENT wait_queue_head_t
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#ifdef CONFIG_CIF_ISP10_REG_TRACE
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int
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cif_isp10_pltfrm_rtrace_printf(
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struct device *dev,
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const char *fmt,
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...);
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int
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cif_isp10_pltfrm_ftrace_printf(
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struct device *dev,
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const char *fmt,
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...);
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#else
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#define cif_isp10_pltfrm_rtrace_printf(dev, str, ...)
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#define cif_isp10_pltfrm_ftrace_printf(dev, str, ...)
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#endif
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#define cif_isp10_pltfrm_pr_dbg(dev, fmt, arg...) \
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do { \
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pr_debug("%s: " fmt, \
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__func__, ## arg); \
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cif_isp10_pltfrm_ftrace_printf(dev, "%s: " fmt, \
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__func__, ## arg); \
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} while (0)
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#define cif_isp10_pltfrm_pr_info(dev, fmt, arg...) \
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do { \
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pr_info("%s: " fmt, \
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__func__, ## arg); \
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cif_isp10_pltfrm_ftrace_printf(dev, "%s: " fmt, \
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__func__, ## arg); \
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} while (0)
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#define cif_isp10_pltfrm_pr_warn(dev, fmt, arg...) \
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do { \
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pr_warn("%s WARN: " fmt, \
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__func__, ## arg); \
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cif_isp10_pltfrm_ftrace_printf(dev, "%s WARN: " fmt, \
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__func__, ## arg); \
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} while (0)
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#define cif_isp10_pltfrm_pr_err(dev, fmt, arg...) \
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do { \
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pr_err("%s(%d) ERR: " fmt, \
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__func__, __LINE__, ## arg); \
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cif_isp10_pltfrm_ftrace_printf(dev, "%s(%d) ERR: " fmt, \
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__func__, __LINE__, ## arg); \
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} while (0)
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void cif_isp10_pltfrm_write_reg(
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struct device *dev,
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u32 data,
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CIF_ISP10_PLTFRM_MEM_IO_ADDR addr);
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void cif_isp10_pltfrm_write_reg_OR(
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struct device *dev,
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u32 data,
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CIF_ISP10_PLTFRM_MEM_IO_ADDR addr);
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void cif_isp10_pltfrm_write_reg_AND(
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struct device *dev,
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u32 data,
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CIF_ISP10_PLTFRM_MEM_IO_ADDR addr);
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u32 cif_isp10_pltfrm_read_reg(
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struct device *dev,
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CIF_ISP10_PLTFRM_MEM_IO_ADDR addr);
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#define cif_iowrite32(d, a) \
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cif_isp10_pltfrm_write_reg(NULL, (u32)(d), a)
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#define cif_ioread32(a) \
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cif_isp10_pltfrm_read_reg(NULL, a)
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#define cif_iowrite32OR(d, a) \
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cif_isp10_pltfrm_write_reg_OR(NULL, (u32)(d), a)
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#define cif_iowrite32AND(d, a) \
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cif_isp10_pltfrm_write_reg_AND(NULL, (u32)(d), a)
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/* BUG: Register write seems to fail sometimes w/o read before write. */
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#define cif_iowrite32_verify(d, a, mask) \
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{ \
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unsigned int i = 0; \
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unsigned long flags = 0; \
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spin_lock_irqsave(&dev->iowrite32_verify_lock, flags); \
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do { \
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cif_iowrite32(d, a); \
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udelay(1); \
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if (i++ == 50) { \
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pr_err("Error in writing %x@0x%p, read %x\n", \
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(d) & (mask), a, ioread32(a)); \
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WARN_ON(1); \
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} \
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} while ((ioread32(a) & mask) != ((d) & mask)); \
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spin_unlock_irqrestore(&dev->iowrite32_verify_lock, flags);\
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}
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#define cif_iowrite32OR_verify(d, a, mask) \
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cif_iowrite32_verify((u32)(d) | cif_ioread32(a), a, mask)
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#define cif_iowrite32AND_verify(d, a, mask) \
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cif_iowrite32_verify((u32)(d) & cif_ioread32(a), a, mask)
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#define cif_isp10_pltfrm_event_init(_dev, _event) \
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init_waitqueue_head(_event)
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#define cif_isp10_pltfrm_event_clear(_dev, _event)
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#define cif_isp10_pltfrm_event_signal(_dev, _event) \
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wake_up_interruptible(_event)
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#define cif_isp10_pltfrm_event_wait_timeout( \
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_dev, _event, _condition, _timeout_us) \
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wait_event_interruptible_timeout( \
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*(_event), _condition, ((_timeout_us) * HZ) / 1000000)
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void
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cif_isp10_pltfrm_debug_register_print_cb(
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struct device *dev,
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void (*print)(void *cntxt, const char *block_name),
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void *cntxt);
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int cif_isp10_pltfrm_dev_init(
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struct cif_isp10_device *cif_isp_dev,
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struct device **dev,
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void __iomem **reg_base_addr);
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void cif_isp10_pltfrm_dev_release(
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struct device *dev,
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struct cif_isp10_device *cif_isp10_dev);
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int cif_isp10_pltfrm_pm_set_state(
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struct device *dev,
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enum cif_isp10_pm_state state);
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int cif_isp10_pltfrm_write_cif_ana_bandgap_bias(
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struct device *dev,
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u32 val);
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int cif_isp10_pltfrm_pinctrl_set_state(
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struct device *dev,
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enum cif_isp10_pinctrl_state pinctrl_state);
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int cif_isp10_pltfrm_get_img_src_device(
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struct device *dev,
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struct cif_isp10_img_src **img_src_array,
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unsigned int array_len);
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int cif_isp10_pltfrm_g_interface_config(
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struct cif_isp10_img_src *img_src,
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struct pltfrm_cam_itf *cam_itf);
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int cif_isp10_pltfrm_irq_register_isr(
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struct device *dev,
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unsigned int mis,
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int (*isr)(unsigned int mis, void *cntxt),
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void *cntxt);
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const char *cif_isp10_pltfrm_get_device_type(
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struct device *dev);
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const char *cif_isp10_pltfrm_dev_string(
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struct device *dev);
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int cif_isp10_pltfrm_soc_init(
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struct cif_isp10_device *cif_isp10_dev,
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struct pltfrm_soc_cfg *soc_cfg);
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int cif_isp10_pltfrm_mipi_dphy_config(
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struct cif_isp10_device *cif_isp10_dev);
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int cif_isp10_pltfrm_reset(
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struct cif_isp10_device *cif_isp10_dev);
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#endif
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