/* SPDX-License-Identifier: GPL-2.0 */
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/* DMA controller registers */
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#define REG8_1(a0) ((const u16[8]) { a0, a0 + 1, a0 + 2, a0 + 3, \
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a0 + 4, a0 + 5, a0 + 6, a0 + 7})
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#define REG8_2(a0) ((const u16[8]) { a0, a0 + 2, a0 + 4, a0 + 6, \
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a0 + 8, a0 + 0xa, a0 + 0xc, a0 + 0xe})
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#define REG8_8(a0) ((const u16[8]) { a0, a0 + 8, a0 + 0x10, a0 + 0x18, \
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a0 + 0x20, a0 + 0x28, a0 + 0x30, \
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a0 + 0x38})
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#define INT_STATUS 0x00
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#define PB_STATUS 0x01
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#define DMA_CMD 0x02
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#define VIDEO_FIFO_STATUS 0x03
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#define VIDEO_CHANNEL_ID 0x04
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#define VIDEO_PARSER_STATUS 0x05
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#define SYS_SOFT_RST 0x06
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#define DMA_PAGE_TABLE0_ADDR ((const u16[8]) { 0x08, 0xd0, 0xd2, 0xd4, \
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0xd6, 0xd8, 0xda, 0xdc })
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#define DMA_PAGE_TABLE1_ADDR ((const u16[8]) { 0x09, 0xd1, 0xd3, 0xd5, \
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0xd7, 0xd9, 0xdb, 0xdd })
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#define DMA_CHANNEL_ENABLE 0x0a
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#define DMA_CONFIG 0x0b
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#define DMA_TIMER_INTERVAL 0x0c
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#define DMA_CHANNEL_TIMEOUT 0x0d
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#define VDMA_CHANNEL_CONFIG REG8_1(0x10)
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#define ADMA_P_ADDR REG8_2(0x18)
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#define ADMA_B_ADDR REG8_2(0x19)
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#define DMA10_P_ADDR 0x28
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#define DMA10_B_ADDR 0x29
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#define VIDEO_CONTROL1 0x2a
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#define VIDEO_CONTROL2 0x2b
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#define AUDIO_CONTROL1 0x2c
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#define AUDIO_CONTROL2 0x2d
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#define PHASE_REF 0x2e
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#define GPIO_REG 0x2f
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#define INTL_HBAR_CTRL REG8_1(0x30)
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#define AUDIO_CONTROL3 0x38
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#define VIDEO_FIELD_CTRL REG8_1(0x39)
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#define HSCALER_CTRL REG8_1(0x42)
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#define VIDEO_SIZE REG8_1(0x4A)
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#define VIDEO_SIZE_F2 REG8_1(0x52)
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#define MD_CONF REG8_1(0x60)
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#define MD_INIT REG8_1(0x68)
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#define MD_MAP0 REG8_1(0x70)
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#define VDMA_P_ADDR REG8_8(0x80) /* not used in DMA SG mode */
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#define VDMA_WHP REG8_8(0x81)
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#define VDMA_B_ADDR REG8_8(0x82)
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#define VDMA_F2_P_ADDR REG8_8(0x84)
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#define VDMA_F2_WHP REG8_8(0x85)
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#define VDMA_F2_B_ADDR REG8_8(0x86)
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#define EP_REG_ADDR 0xfe
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#define EP_REG_DATA 0xff
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/* Video decoder registers */
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#define VDREG8(a0) ((const u16[8]) { \
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a0 + 0x000, a0 + 0x010, a0 + 0x020, a0 + 0x030, \
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a0 + 0x100, a0 + 0x110, a0 + 0x120, a0 + 0x130})
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#define VIDSTAT VDREG8(0x100)
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#define BRIGHT VDREG8(0x101)
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#define CONTRAST VDREG8(0x102)
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#define SHARPNESS VDREG8(0x103)
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#define SAT_U VDREG8(0x104)
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#define SAT_V VDREG8(0x105)
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#define HUE VDREG8(0x106)
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#define CROP_HI VDREG8(0x107)
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#define VDELAY_LO VDREG8(0x108)
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#define VACTIVE_LO VDREG8(0x109)
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#define HDELAY_LO VDREG8(0x10a)
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#define HACTIVE_LO VDREG8(0x10b)
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#define MVSN VDREG8(0x10c)
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#define STATUS2 VDREG8(0x10d)
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#define SDT VDREG8(0x10e)
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#define SDT_EN VDREG8(0x10f)
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#define VSCALE_LO VDREG8(0x144)
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#define SCALE_HI VDREG8(0x145)
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#define HSCALE_LO VDREG8(0x146)
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#define F2CROP_HI VDREG8(0x147)
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#define F2VDELAY_LO VDREG8(0x148)
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#define F2VACTIVE_LO VDREG8(0x149)
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#define F2HDELAY_LO VDREG8(0x14a)
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#define F2HACTIVE_LO VDREG8(0x14b)
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#define F2VSCALE_LO VDREG8(0x14c)
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#define F2SCALE_HI VDREG8(0x14d)
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#define F2HSCALE_LO VDREG8(0x14e)
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#define F2CNT VDREG8(0x14f)
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#define VDREG2(a0) ((const u16[2]) { a0, a0 + 0x100 })
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#define SRST VDREG2(0x180)
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#define ACNTL VDREG2(0x181)
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#define ACNTL2 VDREG2(0x182)
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#define CNTRL1 VDREG2(0x183)
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#define CKHY VDREG2(0x184)
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#define SHCOR VDREG2(0x185)
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#define CORING VDREG2(0x186)
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#define CLMPG VDREG2(0x187)
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#define IAGC VDREG2(0x188)
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#define VCTRL1 VDREG2(0x18f)
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#define MISC1 VDREG2(0x194)
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#define LOOP VDREG2(0x195)
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#define MISC2 VDREG2(0x196)
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#define CLMD VDREG2(0x197)
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#define ANPWRDOWN VDREG2(0x1ce)
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#define AIGAIN ((const u16[8]) { 0x1d0, 0x1d1, 0x1d2, 0x1d3, \
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0x2d0, 0x2d1, 0x2d2, 0x2d3 })
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#define SYS_MODE_DMA_SHIFT 13
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#define AUDIO_DMA_SIZE_SHIFT 19
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#define AUDIO_DMA_SIZE_MIN SZ_512
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#define AUDIO_DMA_SIZE_MAX SZ_4K
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#define AUDIO_DMA_SIZE_MASK (SZ_8K - 1)
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#define DMA_CMD_ENABLE BIT(31)
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#define INT_STATUS_DMA_TOUT BIT(17)
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#define TW686X_VIDSTAT_HLOCK BIT(6)
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#define TW686X_VIDSTAT_VDLOSS BIT(7)
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#define TW686X_STD_NTSC_M 0
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#define TW686X_STD_PAL 1
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#define TW686X_STD_SECAM 2
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#define TW686X_STD_NTSC_443 3
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#define TW686X_STD_PAL_M 4
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#define TW686X_STD_PAL_CN 5
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#define TW686X_STD_PAL_60 6
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#define TW686X_FIELD_MODE 0x3
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#define TW686X_FRAME_MODE 0x2
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/* 0x1 is reserved */
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#define TW686X_SG_MODE 0x0
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#define TW686X_FIFO_ERROR(x) (x & ~(0xff))
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