/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2021 Rockchip Electronics Co. Ltd.
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*
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* Author: Dingxian Wen <shawn.wen@rock-chips.com>
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*/
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#ifndef _LT8619C_H
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#define _LT8619C_H
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/* --------------- configuration -------------------- */
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#define CLK_SRC XTAL_CLK
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#define REF_RESISTANCE EXT_RESISTANCE
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#define CP_CONVERT_MODE HDPC
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#define YUV_COLORDEPTH OUTPUT_16BIT_LOW
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#define BT_TX_SYNC_POL BT_TX_SYNC_POSITIVE
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/* -------------------------------------------------- */
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#define LT8619C_CHIPID 0x1604B0
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#define EDID_NUM_BLOCKS_MAX 2
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#define EDID_BLOCK_SIZE 128
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#define POLL_INTERVAL_MS 1000
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#define lt8619c_PIXEL_RATE 400000000
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#define BANK_REG 0xff
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#define BANK_60 0x60
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#define BANK_80 0x80
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#define CHIPID_REG_H 0x00
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#define CHIPID_REG_M 0x01
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#define CHIPID_REG_L 0x02
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#define LT8619C_MAX_REGISTER 0xff
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#define WAIT_MAX_TIMES 10
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#define BT656_OUTPUT 0x04
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#define BT1120_OUTPUT 0x03
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#define BT1120_8BIT_OUTPUT 0x05
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#define BT_TX_SYNC_POSITIVE 0x30
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#define BT_TX_SYNC_NEGATIVE 0x00
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#define PROGRESSIVE_INDICATOR 0x00
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#define INTERLACE_INDICATOR 0x08
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/* 0x08: Use xtal clk; 0x18: Use internal clk */
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#define XTAL_CLK 0x08
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#define INT_CLK 0x18
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/* internal resistance */
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#define INT_RESISTANCE 0x88
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/* external resistance(Pin 16 - REXT, 2K resistance) */
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#define EXT_RESISTANCE 0x80
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#define CLK_SDRMODE 0
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/* CLK divided by 2 */
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#define CLK_DDRMODE 1
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#define SDTV 0x00
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#define SDPC 0x10
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#define HDTV 0x20
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#define HDPC 0x30
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/*
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* enable
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* D0 ~ D7 Y ; D8 ~ D15 C
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* D8 ~ D15 Y ; D16 ~ D23 C
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*/
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#define YC_SWAP_EN 0x08
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/*
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* disable
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* D0 ~ D7 C ; D8 ~ D15 Y
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* D8 ~ D15 C ; D16 ~ D23 Y
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*/
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#define YC_SWAP_DIS 0x00
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/*
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* BT1120 24bit / BT656 12bit
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* when YC_SWAP_EN:
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* BT656 12bit D0 ~ D11
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* BT1120 24bit : D0 ~ D11 Y ; D12 ~ D23 C
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* when YC_SWAP_DIS:
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* BT656 12bit D12 ~ D23
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* BT1120 24bit : D0 ~ D11 C ; D12 ~ D23 Y
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*/
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#define OUTPUT_24BIT 0x00
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/*
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* BT1120 20bit / BT656 10bit
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* when YC_SWAP_EN:
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* BT656 10bit D4 ~ D13
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* BT1120 20bit : D4 ~ D13 Y ; D14 ~ D23 C
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* when YC_SWAP_DIS:
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* BT656 10bit D14 ~ D23
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* BT1120 20bit : D4 ~ D13 C ; D14 ~ D23 Y
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*/
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#define OUTPUT_20BIT_HIGH 0x04
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/*
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* when YC_SWAP_EN:
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* BT656 10bit D0 ~ D9
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* BT1120 20bit : D0 ~ D9 Y ; D10 ~ D19 C
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* when YC_SWAP_DIS:
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* BT656 10bit D10 ~ D19
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* BT1120 20bit : D0 ~ D9 C ; D10 ~ D19 Y
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*/
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#define OUTPUT_20BIT_LOW 0x05
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/*
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* BT1120 16bit / BT656 8bit
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* when YC_SWAP_EN:
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* BT656 8bit D8 ~ D15
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* BT1120 16bit : D8 ~ D15 Y ; D16 ~ D23 C
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* when YC_SWAP_DIS:
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* BT656 8bit D16 ~ D23
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* BT1120 16bit : D8 ~ D15 C ; D16 ~ D23 Y
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*/
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#define OUTPUT_16BIT_HIGH 0x06
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/*
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* when YC_SWAP_EN:
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* BT656 8bit D0 ~ D7
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* BT1120 16bit : D0 ~ D7 Y ; D8 ~ D15 C
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* when YC_SWAP_DIS:
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* BT656 8bit D8 ~ D15
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* BT1120 16bit : D0 ~ D7 C ; D8 ~ D15 Y
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*/
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#define OUTPUT_16BIT_LOW 0x07
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/* ---------------- regs ----------------- */
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/* reg: 0x60_60 */
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#define SYNC_POL_MASK GENMASK(5, 4)
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#define IP_SEL_MASK GENMASK(3, 3)
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#define OUTPUT_MODE_MASK GENMASK(2, 0)
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/* reg: 0x80_05 */
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#define RGD_HS_POL_ADJ_MASK GENMASK(5, 5)
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#define RGD_VS_POL_ADJ_MASK GENMASK(4, 4)
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/* reg: 0x80_17 */
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#define RGOD_VID_HSPOL BIT(7)
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#define RGOD_VID_VSPOL BIT(6)
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#endif
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