//
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// Accelerated CRC-T10DIF using arm64 NEON and Crypto Extensions instructions
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//
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// Copyright (C) 2016 Linaro Ltd <ard.biesheuvel@linaro.org>
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License version 2 as
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// published by the Free Software Foundation.
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//
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//
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// Implement fast CRC-T10DIF computation with SSE and PCLMULQDQ instructions
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//
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// Copyright (c) 2013, Intel Corporation
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//
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// Authors:
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// Erdinc Ozturk <erdinc.ozturk@intel.com>
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// Vinodh Gopal <vinodh.gopal@intel.com>
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// James Guilford <james.guilford@intel.com>
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// Tim Chen <tim.c.chen@linux.intel.com>
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//
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// This software is available to you under a choice of one of two
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// licenses. You may choose to be licensed under the terms of the GNU
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// General Public License (GPL) Version 2, available from the file
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// COPYING in the main directory of this source tree, or the
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// OpenIB.org BSD license below:
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// * Neither the name of the Intel Corporation nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY INTEL CORPORATION ""AS IS"" AND ANY
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// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL CORPORATION OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Function API:
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// UINT16 crc_t10dif_pcl(
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// UINT16 init_crc, //initial CRC value, 16 bits
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// const unsigned char *buf, //buffer pointer to calculate CRC on
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// UINT64 len //buffer length in bytes (64-bit data)
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// );
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//
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// Reference paper titled "Fast CRC Computation for Generic
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// Polynomials Using PCLMULQDQ Instruction"
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// URL: http://www.intel.com/content/dam/www/public/us/en/documents
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// /white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf
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//
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//
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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.text
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.cpu generic+crypto
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arg1_low32 .req w19
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arg2 .req x20
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arg3 .req x21
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vzr .req v13
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ENTRY(crc_t10dif_pmull)
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frame_push 3, 128
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mov arg1_low32, w0
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mov arg2, x1
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mov arg3, x2
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movi vzr.16b, #0 // init zero register
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// adjust the 16-bit initial_crc value, scale it to 32 bits
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lsl arg1_low32, arg1_low32, #16
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// check if smaller than 256
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cmp arg3, #256
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// for sizes less than 128, we can't fold 64B at a time...
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b.lt _less_than_128
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// load the initial crc value
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// crc value does not need to be byte-reflected, but it needs
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// to be moved to the high part of the register.
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// because data will be byte-reflected and will align with
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// initial crc at correct place.
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movi v10.16b, #0
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mov v10.s[3], arg1_low32 // initial crc
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// receive the initial 64B data, xor the initial crc value
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ldp q0, q1, [arg2]
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ldp q2, q3, [arg2, #0x20]
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ldp q4, q5, [arg2, #0x40]
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ldp q6, q7, [arg2, #0x60]
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add arg2, arg2, #0x80
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CPU_LE( rev64 v0.16b, v0.16b )
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CPU_LE( rev64 v1.16b, v1.16b )
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CPU_LE( rev64 v2.16b, v2.16b )
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CPU_LE( rev64 v3.16b, v3.16b )
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CPU_LE( rev64 v4.16b, v4.16b )
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CPU_LE( rev64 v5.16b, v5.16b )
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CPU_LE( rev64 v6.16b, v6.16b )
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CPU_LE( rev64 v7.16b, v7.16b )
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CPU_LE( ext v0.16b, v0.16b, v0.16b, #8 )
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CPU_LE( ext v1.16b, v1.16b, v1.16b, #8 )
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CPU_LE( ext v2.16b, v2.16b, v2.16b, #8 )
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CPU_LE( ext v3.16b, v3.16b, v3.16b, #8 )
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CPU_LE( ext v4.16b, v4.16b, v4.16b, #8 )
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CPU_LE( ext v5.16b, v5.16b, v5.16b, #8 )
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CPU_LE( ext v6.16b, v6.16b, v6.16b, #8 )
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CPU_LE( ext v7.16b, v7.16b, v7.16b, #8 )
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// XOR the initial_crc value
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eor v0.16b, v0.16b, v10.16b
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ldr_l q10, rk3, x8 // xmm10 has rk3 and rk4
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// type of pmull instruction
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// will determine which constant to use
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//
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// we subtract 256 instead of 128 to save one instruction from the loop
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//
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sub arg3, arg3, #256
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// at this section of the code, there is 64*x+y (0<=y<64) bytes of
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// buffer. The _fold_64_B_loop will fold 64B at a time
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// until we have 64+y Bytes of buffer
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// fold 64B at a time. This section of the code folds 4 vector
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// registers in parallel
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_fold_64_B_loop:
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.macro fold64, reg1, reg2
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ldp q11, q12, [arg2], #0x20
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pmull2 v8.1q, \reg1\().2d, v10.2d
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pmull \reg1\().1q, \reg1\().1d, v10.1d
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CPU_LE( rev64 v11.16b, v11.16b )
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CPU_LE( rev64 v12.16b, v12.16b )
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pmull2 v9.1q, \reg2\().2d, v10.2d
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pmull \reg2\().1q, \reg2\().1d, v10.1d
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CPU_LE( ext v11.16b, v11.16b, v11.16b, #8 )
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CPU_LE( ext v12.16b, v12.16b, v12.16b, #8 )
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eor \reg1\().16b, \reg1\().16b, v8.16b
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eor \reg2\().16b, \reg2\().16b, v9.16b
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eor \reg1\().16b, \reg1\().16b, v11.16b
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eor \reg2\().16b, \reg2\().16b, v12.16b
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.endm
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fold64 v0, v1
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fold64 v2, v3
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fold64 v4, v5
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fold64 v6, v7
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subs arg3, arg3, #128
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// check if there is another 64B in the buffer to be able to fold
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b.lt _fold_64_B_end
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if_will_cond_yield_neon
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stp q0, q1, [sp, #.Lframe_local_offset]
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stp q2, q3, [sp, #.Lframe_local_offset + 32]
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stp q4, q5, [sp, #.Lframe_local_offset + 64]
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stp q6, q7, [sp, #.Lframe_local_offset + 96]
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do_cond_yield_neon
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ldp q0, q1, [sp, #.Lframe_local_offset]
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ldp q2, q3, [sp, #.Lframe_local_offset + 32]
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ldp q4, q5, [sp, #.Lframe_local_offset + 64]
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ldp q6, q7, [sp, #.Lframe_local_offset + 96]
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ldr_l q10, rk3, x8
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movi vzr.16b, #0 // init zero register
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endif_yield_neon
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b _fold_64_B_loop
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_fold_64_B_end:
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// at this point, the buffer pointer is pointing at the last y Bytes
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// of the buffer the 64B of folded data is in 4 of the vector
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// registers: v0, v1, v2, v3
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// fold the 8 vector registers to 1 vector register with different
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// constants
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ldr_l q10, rk9, x8
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.macro fold16, reg, rk
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pmull v8.1q, \reg\().1d, v10.1d
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pmull2 \reg\().1q, \reg\().2d, v10.2d
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.ifnb \rk
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ldr_l q10, \rk, x8
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.endif
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eor v7.16b, v7.16b, v8.16b
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eor v7.16b, v7.16b, \reg\().16b
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.endm
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fold16 v0, rk11
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fold16 v1, rk13
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fold16 v2, rk15
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fold16 v3, rk17
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fold16 v4, rk19
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fold16 v5, rk1
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fold16 v6
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// instead of 64, we add 48 to the loop counter to save 1 instruction
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// from the loop instead of a cmp instruction, we use the negative
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// flag with the jl instruction
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adds arg3, arg3, #(128-16)
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b.lt _final_reduction_for_128
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// now we have 16+y bytes left to reduce. 16 Bytes is in register v7
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// and the rest is in memory. We can fold 16 bytes at a time if y>=16
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// continue folding 16B at a time
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_16B_reduction_loop:
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pmull v8.1q, v7.1d, v10.1d
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pmull2 v7.1q, v7.2d, v10.2d
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eor v7.16b, v7.16b, v8.16b
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ldr q0, [arg2], #16
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CPU_LE( rev64 v0.16b, v0.16b )
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CPU_LE( ext v0.16b, v0.16b, v0.16b, #8 )
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eor v7.16b, v7.16b, v0.16b
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subs arg3, arg3, #16
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// instead of a cmp instruction, we utilize the flags with the
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// jge instruction equivalent of: cmp arg3, 16-16
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// check if there is any more 16B in the buffer to be able to fold
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b.ge _16B_reduction_loop
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// now we have 16+z bytes left to reduce, where 0<= z < 16.
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// first, we reduce the data in the xmm7 register
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_final_reduction_for_128:
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// check if any more data to fold. If not, compute the CRC of
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// the final 128 bits
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adds arg3, arg3, #16
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b.eq _128_done
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// here we are getting data that is less than 16 bytes.
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// since we know that there was data before the pointer, we can
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// offset the input pointer before the actual point, to receive
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// exactly 16 bytes. after that the registers need to be adjusted.
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_get_last_two_regs:
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add arg2, arg2, arg3
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ldr q1, [arg2, #-16]
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CPU_LE( rev64 v1.16b, v1.16b )
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CPU_LE( ext v1.16b, v1.16b, v1.16b, #8 )
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// get rid of the extra data that was loaded before
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// load the shift constant
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adr_l x4, tbl_shf_table + 16
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sub x4, x4, arg3
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ld1 {v0.16b}, [x4]
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// shift v2 to the left by arg3 bytes
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tbl v2.16b, {v7.16b}, v0.16b
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// shift v7 to the right by 16-arg3 bytes
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movi v9.16b, #0x80
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eor v0.16b, v0.16b, v9.16b
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tbl v7.16b, {v7.16b}, v0.16b
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// blend
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sshr v0.16b, v0.16b, #7 // convert to 8-bit mask
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bsl v0.16b, v2.16b, v1.16b
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// fold 16 Bytes
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pmull v8.1q, v7.1d, v10.1d
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pmull2 v7.1q, v7.2d, v10.2d
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eor v7.16b, v7.16b, v8.16b
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eor v7.16b, v7.16b, v0.16b
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_128_done:
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// compute crc of a 128-bit value
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ldr_l q10, rk5, x8 // rk5 and rk6 in xmm10
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// 64b fold
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ext v0.16b, vzr.16b, v7.16b, #8
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mov v7.d[0], v7.d[1]
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pmull v7.1q, v7.1d, v10.1d
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eor v7.16b, v7.16b, v0.16b
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// 32b fold
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ext v0.16b, v7.16b, vzr.16b, #4
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mov v7.s[3], vzr.s[0]
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pmull2 v0.1q, v0.2d, v10.2d
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eor v7.16b, v7.16b, v0.16b
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// barrett reduction
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_barrett:
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ldr_l q10, rk7, x8
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mov v0.d[0], v7.d[1]
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pmull v0.1q, v0.1d, v10.1d
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ext v0.16b, vzr.16b, v0.16b, #12
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pmull2 v0.1q, v0.2d, v10.2d
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ext v0.16b, vzr.16b, v0.16b, #12
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eor v7.16b, v7.16b, v0.16b
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mov w0, v7.s[1]
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_cleanup:
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// scale the result back to 16 bits
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lsr x0, x0, #16
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frame_pop
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ret
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_less_than_128:
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cbz arg3, _cleanup
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movi v0.16b, #0
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mov v0.s[3], arg1_low32 // get the initial crc value
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ldr q7, [arg2], #0x10
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CPU_LE( rev64 v7.16b, v7.16b )
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CPU_LE( ext v7.16b, v7.16b, v7.16b, #8 )
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eor v7.16b, v7.16b, v0.16b // xor the initial crc value
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cmp arg3, #16
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b.eq _128_done // exactly 16 left
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b.lt _less_than_16_left
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ldr_l q10, rk1, x8 // rk1 and rk2 in xmm10
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// update the counter. subtract 32 instead of 16 to save one
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// instruction from the loop
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subs arg3, arg3, #32
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b.ge _16B_reduction_loop
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add arg3, arg3, #16
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b _get_last_two_regs
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_less_than_16_left:
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// shl r9, 4
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adr_l x0, tbl_shf_table + 16
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sub x0, x0, arg3
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ld1 {v0.16b}, [x0]
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movi v9.16b, #0x80
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eor v0.16b, v0.16b, v9.16b
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tbl v7.16b, {v7.16b}, v0.16b
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b _128_done
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ENDPROC(crc_t10dif_pmull)
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// precomputed constants
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// these constants are precomputed from the poly:
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// 0x8bb70000 (0x8bb7 scaled to 32 bits)
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.section ".rodata", "a"
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.align 4
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// Q = 0x18BB70000
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// rk1 = 2^(32*3) mod Q << 32
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// rk2 = 2^(32*5) mod Q << 32
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// rk3 = 2^(32*15) mod Q << 32
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// rk4 = 2^(32*17) mod Q << 32
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// rk5 = 2^(32*3) mod Q << 32
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// rk6 = 2^(32*2) mod Q << 32
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// rk7 = floor(2^64/Q)
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// rk8 = Q
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rk1: .octa 0x06df0000000000002d56000000000000
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rk3: .octa 0x7cf50000000000009d9d000000000000
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rk5: .octa 0x13680000000000002d56000000000000
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rk7: .octa 0x000000018bb7000000000001f65a57f8
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rk9: .octa 0xbfd6000000000000ceae000000000000
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rk11: .octa 0x713c0000000000001e16000000000000
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rk13: .octa 0x80a6000000000000f7f9000000000000
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rk15: .octa 0xe658000000000000044c000000000000
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rk17: .octa 0xa497000000000000ad18000000000000
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rk19: .octa 0xe7b50000000000006ee3000000000000
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tbl_shf_table:
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// use these values for shift constants for the tbl/tbx instruction
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// different alignments result in values as shown:
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// DDQ 0x008f8e8d8c8b8a898887868584838281 # shl 15 (16-1) / shr1
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// DDQ 0x01008f8e8d8c8b8a8988878685848382 # shl 14 (16-3) / shr2
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// DDQ 0x0201008f8e8d8c8b8a89888786858483 # shl 13 (16-4) / shr3
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// DDQ 0x030201008f8e8d8c8b8a898887868584 # shl 12 (16-4) / shr4
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// DDQ 0x04030201008f8e8d8c8b8a8988878685 # shl 11 (16-5) / shr5
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// DDQ 0x0504030201008f8e8d8c8b8a89888786 # shl 10 (16-6) / shr6
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// DDQ 0x060504030201008f8e8d8c8b8a898887 # shl 9 (16-7) / shr7
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// DDQ 0x07060504030201008f8e8d8c8b8a8988 # shl 8 (16-8) / shr8
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// DDQ 0x0807060504030201008f8e8d8c8b8a89 # shl 7 (16-9) / shr9
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// DDQ 0x090807060504030201008f8e8d8c8b8a # shl 6 (16-10) / shr10
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// DDQ 0x0a090807060504030201008f8e8d8c8b # shl 5 (16-11) / shr11
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// DDQ 0x0b0a090807060504030201008f8e8d8c # shl 4 (16-12) / shr12
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// DDQ 0x0c0b0a090807060504030201008f8e8d # shl 3 (16-13) / shr13
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// DDQ 0x0d0c0b0a090807060504030201008f8e # shl 2 (16-14) / shr14
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// DDQ 0x0e0d0c0b0a090807060504030201008f # shl 1 (16-15) / shr15
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.byte 0x0, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87
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.byte 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f
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.byte 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7
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.byte 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe , 0x0
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