/*
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* Copyright 2020 Rockchip Electronics Co. LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __MPP_DEVICE_H__
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#define __MPP_DEVICE_H__
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#include "mpp_err.h"
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#include "mpp_dev_defs.h"
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#include "mpp_callback.h"
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typedef enum MppDevIoctlCmd_e {
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/* device batch mode config */
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MPP_DEV_BATCH_ON,
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MPP_DEV_BATCH_OFF,
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MPP_DEV_DELIMIT,
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MPP_DEV_SET_CB_CTX,
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/* hardware operation setup config */
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MPP_DEV_REG_WR,
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MPP_DEV_REG_RD,
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MPP_DEV_REG_OFFSET,
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MPP_DEV_REG_OFFS,
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MPP_DEV_RCB_INFO,
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MPP_DEV_SET_INFO,
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MPP_DEV_CMD_SEND,
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MPP_DEV_CMD_POLL,
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MPP_DEV_IOCTL_CMD_BUTT,
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} MppDevIoctlCmd;
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/* for MPP_DEV_REG_WR */
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typedef struct MppDevRegWrCfg_t {
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void *reg;
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RK_U32 size;
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RK_U32 offset;
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} MppDevRegWrCfg;
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/* for MPP_DEV_REG_RD */
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typedef struct MppDevRegRdCfg_t {
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void *reg;
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RK_U32 size;
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RK_U32 offset;
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} MppDevRegRdCfg;
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/* for MPP_DEV_REG_OFFSET */
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typedef struct MppDevRegOffsetCfg_t {
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RK_U32 reg_idx;
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RK_U32 offset;
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} MppDevRegOffsetCfg;
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/* for multi MPP_DEV_REG_OFFSET */
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typedef struct MppDevRegOffsCfg_t {
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RK_S32 size;
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RK_S32 count;
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MppDevRegOffsetCfg cfgs[];
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} MppDevRegOffCfgs;
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/* for MPP_DEV_RCB_INFO */
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typedef struct MppDevRcbInfoCfg_t {
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RK_U32 reg_idx;
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RK_U32 size;
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} MppDevRcbInfoCfg;
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/* for MPP_DEV_SET_INFO */
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typedef struct MppDevSetInfoCfg_t {
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RK_U32 type;
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RK_U32 flag;
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RK_U64 data;
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} MppDevInfoCfg;
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typedef union MppDevPollEncSliceInfo_u {
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RK_U32 val;
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struct {
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RK_U32 length : 31;
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RK_U32 last : 1;
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};
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} MppDevPollEncSliceInfo;
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/* for MPP_DEV_POLL */
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typedef struct MppDevPollCfg_t {
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RK_S32 poll_type;
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RK_S32 poll_ret;
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RK_S32 count_max;
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RK_S32 count_ret;
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MppDevPollEncSliceInfo slice_info[];
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} MppDevPollCfg;
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typedef struct MppDevApi_t {
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const char *name;
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RK_U32 ctx_size;
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MPP_RET (*init)(void *ctx, MppClientType type);
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MPP_RET (*deinit)(void *ctx);
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/* bat mode function */
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MPP_RET (*attach)(void *ctx);
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MPP_RET (*detach)(void *ctx);
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MPP_RET (*delimit)(void *ctx);
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MPP_RET (*set_cb_ctx)(void *ctx, MppCbCtx *cb);
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/* config the cmd on preparing */
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MPP_RET (*reg_wr)(void *ctx, MppDevRegWrCfg *cfg);
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MPP_RET (*reg_rd)(void *ctx, MppDevRegRdCfg *cfg);
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MPP_RET (*reg_offset)(void *ctx, MppDevRegOffsetCfg *cfg);
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MPP_RET (*reg_offs)(void *ctx, MppDevRegOffCfgs *cfg);
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MPP_RET (*rcb_info)(void *ctx, MppDevRcbInfoCfg *cfg);
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MPP_RET (*set_info)(void *ctx, MppDevInfoCfg *cfg);
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/* send cmd to hardware */
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MPP_RET (*cmd_send)(void *ctx);
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/* poll cmd from hardware */
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MPP_RET (*cmd_poll)(void *ctx, MppDevPollCfg *cfg);
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} MppDevApi;
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typedef void* MppDev;
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#ifdef __cplusplus
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extern "C" {
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#endif
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MPP_RET mpp_dev_init(MppDev *ctx, MppClientType type);
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MPP_RET mpp_dev_deinit(MppDev ctx);
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MPP_RET mpp_dev_ioctl(MppDev ctx, RK_S32 cmd, void *param);
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/* special helper function for large address offset config */
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MPP_RET mpp_dev_set_reg_offset(MppDev dev, RK_S32 index, RK_U32 offset);
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/* register offset multi config */
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MPP_RET mpp_dev_multi_offset_init(MppDevRegOffCfgs **cfgs, RK_S32 size);
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MPP_RET mpp_dev_multi_offset_deinit(MppDevRegOffCfgs *cfgs);
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MPP_RET mpp_dev_multi_offset_reset(MppDevRegOffCfgs *cfgs);
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MPP_RET mpp_dev_multi_offset_update(MppDevRegOffCfgs *cfgs, RK_S32 index, RK_U32 offset);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __MPP_DEVICE_H__ */
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