/*
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* cros_ec_lpc_mec - LPC variant I/O for Microchip EC
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*
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* Copyright (C) 2016 Google, Inc
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* This driver uses the Chrome OS EC byte-level message-based protocol for
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* communicating the keyboard state (which keys are pressed) from a keyboard EC
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* to the AP over some bus (such as i2c, lpc, spi). The EC does debouncing,
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* but everything else (including deghosting) is done here. The main
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* motivation for this is to keep the EC firmware as simple as possible, since
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* it cannot be easily upgraded and EC flash/IRAM space is relatively
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* expensive.
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*/
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#ifndef __LINUX_MFD_CROS_EC_MEC_H
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#define __LINUX_MFD_CROS_EC_MEC_H
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#include <linux/mfd/cros_ec_commands.h>
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enum cros_ec_lpc_mec_emi_access_mode {
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/* 8-bit access */
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ACCESS_TYPE_BYTE = 0x0,
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/* 16-bit access */
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ACCESS_TYPE_WORD = 0x1,
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/* 32-bit access */
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ACCESS_TYPE_LONG = 0x2,
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/*
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* 32-bit access, read or write of MEC_EMI_EC_DATA_B3 causes the
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* EC data register to be incremented.
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*/
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ACCESS_TYPE_LONG_AUTO_INCREMENT = 0x3,
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};
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enum cros_ec_lpc_mec_io_type {
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MEC_IO_READ,
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MEC_IO_WRITE,
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};
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/* Access IO ranges 0x800 thru 0x9ff using EMI interface instead of LPC */
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#define MEC_EMI_RANGE_START EC_HOST_CMD_REGION0
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#define MEC_EMI_RANGE_END (EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SIZE)
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/* EMI registers are relative to base */
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#define MEC_EMI_BASE 0x800
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#define MEC_EMI_HOST_TO_EC (MEC_EMI_BASE + 0)
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#define MEC_EMI_EC_TO_HOST (MEC_EMI_BASE + 1)
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#define MEC_EMI_EC_ADDRESS_B0 (MEC_EMI_BASE + 2)
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#define MEC_EMI_EC_ADDRESS_B1 (MEC_EMI_BASE + 3)
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#define MEC_EMI_EC_DATA_B0 (MEC_EMI_BASE + 4)
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#define MEC_EMI_EC_DATA_B1 (MEC_EMI_BASE + 5)
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#define MEC_EMI_EC_DATA_B2 (MEC_EMI_BASE + 6)
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#define MEC_EMI_EC_DATA_B3 (MEC_EMI_BASE + 7)
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/*
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* cros_ec_lpc_mec_init
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*
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* Initialize MEC I/O.
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*/
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void cros_ec_lpc_mec_init(void);
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/*
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* cros_ec_lpc_mec_destroy
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*
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* Cleanup MEC I/O.
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*/
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void cros_ec_lpc_mec_destroy(void);
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/**
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* cros_ec_lpc_io_bytes_mec - Read / write bytes to MEC EMI port
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*
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* @io_type: MEC_IO_READ or MEC_IO_WRITE, depending on request
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* @offset: Base read / write address
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* @length: Number of bytes to read / write
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* @buf: Destination / source buffer
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*
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* @return 8-bit checksum of all bytes read / written
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*/
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u8 cros_ec_lpc_io_bytes_mec(enum cros_ec_lpc_mec_io_type io_type,
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unsigned int offset, unsigned int length, u8 *buf);
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#endif /* __LINUX_MFD_CROS_EC_MEC_H */
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