/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
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*/
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#ifndef _CORESIGHT_CORESIGHT_ETM_H
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#define _CORESIGHT_CORESIGHT_ETM_H
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#include <asm/local.h>
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#include <linux/spinlock.h>
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#include "coresight-priv.h"
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/*
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* Device registers:
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* 0x000 - 0x2FC: Trace registers
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* 0x300 - 0x314: Management registers
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* 0x318 - 0xEFC: Trace registers
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* 0xF00: Management registers
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* 0xFA0 - 0xFA4: Trace registers
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* 0xFA8 - 0xFFC: Management registers
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*/
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/* Trace registers (0x000-0x2FC) */
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/* Main control and configuration registers */
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#define TRCPRGCTLR 0x004
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#define TRCPROCSELR 0x008
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#define TRCSTATR 0x00C
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#define TRCCONFIGR 0x010
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#define TRCAUXCTLR 0x018
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#define TRCEVENTCTL0R 0x020
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#define TRCEVENTCTL1R 0x024
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#define TRCSTALLCTLR 0x02C
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#define TRCTSCTLR 0x030
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#define TRCSYNCPR 0x034
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#define TRCCCCTLR 0x038
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#define TRCBBCTLR 0x03C
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#define TRCTRACEIDR 0x040
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#define TRCQCTLR 0x044
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/* Filtering control registers */
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#define TRCVICTLR 0x080
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#define TRCVIIECTLR 0x084
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#define TRCVISSCTLR 0x088
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#define TRCVIPCSSCTLR 0x08C
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#define TRCVDCTLR 0x0A0
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#define TRCVDSACCTLR 0x0A4
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#define TRCVDARCCTLR 0x0A8
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/* Derived resources registers */
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#define TRCSEQEVRn(n) (0x100 + (n * 4))
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#define TRCSEQRSTEVR 0x118
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#define TRCSEQSTR 0x11C
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#define TRCEXTINSELR 0x120
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#define TRCCNTRLDVRn(n) (0x140 + (n * 4))
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#define TRCCNTCTLRn(n) (0x150 + (n * 4))
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#define TRCCNTVRn(n) (0x160 + (n * 4))
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/* ID registers */
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#define TRCIDR8 0x180
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#define TRCIDR9 0x184
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#define TRCIDR10 0x188
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#define TRCIDR11 0x18C
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#define TRCIDR12 0x190
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#define TRCIDR13 0x194
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#define TRCIMSPEC0 0x1C0
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#define TRCIMSPECn(n) (0x1C0 + (n * 4))
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#define TRCIDR0 0x1E0
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#define TRCIDR1 0x1E4
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#define TRCIDR2 0x1E8
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#define TRCIDR3 0x1EC
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#define TRCIDR4 0x1F0
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#define TRCIDR5 0x1F4
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#define TRCIDR6 0x1F8
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#define TRCIDR7 0x1FC
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/* Resource selection registers */
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#define TRCRSCTLRn(n) (0x200 + (n * 4))
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/* Single-shot comparator registers */
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#define TRCSSCCRn(n) (0x280 + (n * 4))
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#define TRCSSCSRn(n) (0x2A0 + (n * 4))
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#define TRCSSPCICRn(n) (0x2C0 + (n * 4))
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/* Management registers (0x300-0x314) */
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#define TRCOSLAR 0x300
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#define TRCOSLSR 0x304
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#define TRCPDCR 0x310
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#define TRCPDSR 0x314
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/* Trace registers (0x318-0xEFC) */
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/* Comparator registers */
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#define TRCACVRn(n) (0x400 + (n * 8))
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#define TRCACATRn(n) (0x480 + (n * 8))
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#define TRCDVCVRn(n) (0x500 + (n * 16))
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#define TRCDVCMRn(n) (0x580 + (n * 16))
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#define TRCCIDCVRn(n) (0x600 + (n * 8))
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#define TRCVMIDCVRn(n) (0x640 + (n * 8))
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#define TRCCIDCCTLR0 0x680
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#define TRCCIDCCTLR1 0x684
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#define TRCVMIDCCTLR0 0x688
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#define TRCVMIDCCTLR1 0x68C
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/* Management register (0xF00) */
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/* Integration control registers */
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#define TRCITCTRL 0xF00
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/* Trace registers (0xFA0-0xFA4) */
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/* Claim tag registers */
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#define TRCCLAIMSET 0xFA0
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#define TRCCLAIMCLR 0xFA4
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/* Management registers (0xFA8-0xFFC) */
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#define TRCDEVAFF0 0xFA8
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#define TRCDEVAFF1 0xFAC
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#define TRCLAR 0xFB0
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#define TRCLSR 0xFB4
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#define TRCAUTHSTATUS 0xFB8
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#define TRCDEVARCH 0xFBC
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#define TRCDEVID 0xFC8
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#define TRCDEVTYPE 0xFCC
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#define TRCPIDR4 0xFD0
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#define TRCPIDR5 0xFD4
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#define TRCPIDR6 0xFD8
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#define TRCPIDR7 0xFDC
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#define TRCPIDR0 0xFE0
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#define TRCPIDR1 0xFE4
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#define TRCPIDR2 0xFE8
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#define TRCPIDR3 0xFEC
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#define TRCCIDR0 0xFF0
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#define TRCCIDR1 0xFF4
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#define TRCCIDR2 0xFF8
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#define TRCCIDR3 0xFFC
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/* ETMv4 resources */
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#define ETM_MAX_NR_PE 8
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#define ETMv4_MAX_CNTR 4
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#define ETM_MAX_SEQ_STATES 4
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#define ETM_MAX_EXT_INP_SEL 4
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#define ETM_MAX_EXT_INP 256
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#define ETM_MAX_EXT_OUT 4
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#define ETM_MAX_SINGLE_ADDR_CMP 16
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#define ETM_MAX_ADDR_RANGE_CMP (ETM_MAX_SINGLE_ADDR_CMP / 2)
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#define ETM_MAX_DATA_VAL_CMP 8
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#define ETMv4_MAX_CTXID_CMP 8
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#define ETM_MAX_VMID_CMP 8
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#define ETM_MAX_PE_CMP 8
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#define ETM_MAX_RES_SEL 16
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#define ETM_MAX_SS_CMP 8
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#define ETM_ARCH_V4 0x40
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#define ETMv4_SYNC_MASK 0x1F
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#define ETM_CYC_THRESHOLD_MASK 0xFFF
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#define ETM_CYC_THRESHOLD_DEFAULT 0x100
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#define ETMv4_EVENT_MASK 0xFF
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#define ETM_CNTR_MAX_VAL 0xFFFF
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#define ETM_TRACEID_MASK 0x3f
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/* ETMv4 programming modes */
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#define ETM_MODE_EXCLUDE BIT(0)
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#define ETM_MODE_LOAD BIT(1)
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#define ETM_MODE_STORE BIT(2)
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#define ETM_MODE_LOAD_STORE BIT(3)
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#define ETM_MODE_BB BIT(4)
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#define ETMv4_MODE_CYCACC BIT(5)
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#define ETMv4_MODE_CTXID BIT(6)
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#define ETM_MODE_VMID BIT(7)
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#define ETM_MODE_COND(val) BMVAL(val, 8, 10)
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#define ETMv4_MODE_TIMESTAMP BIT(11)
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#define ETM_MODE_RETURNSTACK BIT(12)
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#define ETM_MODE_QELEM(val) BMVAL(val, 13, 14)
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#define ETM_MODE_DATA_TRACE_ADDR BIT(15)
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#define ETM_MODE_DATA_TRACE_VAL BIT(16)
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#define ETM_MODE_ISTALL BIT(17)
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#define ETM_MODE_DSTALL BIT(18)
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#define ETM_MODE_ATB_TRIGGER BIT(19)
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#define ETM_MODE_LPOVERRIDE BIT(20)
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#define ETM_MODE_ISTALL_EN BIT(21)
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#define ETM_MODE_DSTALL_EN BIT(22)
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#define ETM_MODE_INSTPRIO BIT(23)
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#define ETM_MODE_NOOVERFLOW BIT(24)
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#define ETM_MODE_TRACE_RESET BIT(25)
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#define ETM_MODE_TRACE_ERR BIT(26)
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#define ETM_MODE_VIEWINST_STARTSTOP BIT(27)
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#define ETMv4_MODE_ALL (GENMASK(27, 0) | \
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ETM_MODE_EXCL_KERN | \
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ETM_MODE_EXCL_USER)
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#define TRCSTATR_IDLE_BIT 0
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#define TRCSTATR_PMSTABLE_BIT 1
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#define ETM_DEFAULT_ADDR_COMP 0
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/* PowerDown Control Register bits */
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#define TRCPDCR_PU BIT(3)
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/* secure state access levels */
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#define ETM_EXLEVEL_S_APP BIT(8)
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#define ETM_EXLEVEL_S_OS BIT(9)
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#define ETM_EXLEVEL_S_NA BIT(10)
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#define ETM_EXLEVEL_S_HYP BIT(11)
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/* non-secure state access levels */
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#define ETM_EXLEVEL_NS_APP BIT(12)
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#define ETM_EXLEVEL_NS_OS BIT(13)
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#define ETM_EXLEVEL_NS_HYP BIT(14)
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#define ETM_EXLEVEL_NS_NA BIT(15)
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/**
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* struct etmv4_config - configuration information related to an ETMv4
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* @mode: Controls various modes supported by this ETM.
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* @pe_sel: Controls which PE to trace.
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* @cfg: Controls the tracing options.
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* @eventctrl0: Controls the tracing of arbitrary events.
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* @eventctrl1: Controls the behavior of the events that @event_ctrl0 selects.
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* @stallctl: If functionality that prevents trace unit buffer overflows
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* is available.
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* @ts_ctrl: Controls the insertion of global timestamps in the
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* trace streams.
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* @syncfreq: Controls how often trace synchronization requests occur.
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* the TRCCCCTLR register.
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* @ccctlr: Sets the threshold value for cycle counting.
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* @vinst_ctrl: Controls instruction trace filtering.
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* @viiectlr: Set or read, the address range comparators.
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* @vissctlr: Set, or read, the single address comparators that control the
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* ViewInst start-stop logic.
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* @vipcssctlr: Set, or read, which PE comparator inputs can control the
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* ViewInst start-stop logic.
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* @seq_idx: Sequencor index selector.
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* @seq_ctrl: Control for the sequencer state transition control register.
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* @seq_rst: Moves the sequencer to state 0 when a programmed event occurs.
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* @seq_state: Set, or read the sequencer state.
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* @cntr_idx: Counter index seletor.
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* @cntrldvr: Sets or returns the reload count value for a counter.
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* @cntr_ctrl: Controls the operation of a counter.
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* @cntr_val: Sets or returns the value for a counter.
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* @res_idx: Resource index selector.
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* @res_ctrl: Controls the selection of the resources in the trace unit.
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* @ss_ctrl: Controls the corresponding single-shot comparator resource.
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* @ss_status: The status of the corresponding single-shot comparator.
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* @ss_pe_cmp: Selects the PE comparator inputs for Single-shot control.
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* @addr_idx: Address comparator index selector.
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* @addr_val: Value for address comparator.
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* @addr_acc: Address comparator access type.
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* @addr_type: Current status of the comparator register.
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* @ctxid_idx: Context ID index selector.
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* @ctxid_pid: Value of the context ID comparator.
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* @ctxid_mask0:Context ID comparator mask for comparator 0-3.
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* @ctxid_mask1:Context ID comparator mask for comparator 4-7.
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* @vmid_idx: VM ID index selector.
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* @vmid_val: Value of the VM ID comparator.
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* @vmid_mask0: VM ID comparator mask for comparator 0-3.
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* @vmid_mask1: VM ID comparator mask for comparator 4-7.
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* @ext_inp: External input selection.
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*/
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struct etmv4_config {
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u32 mode;
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u32 pe_sel;
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u32 cfg;
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u32 eventctrl0;
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u32 eventctrl1;
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u32 stall_ctrl;
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u32 ts_ctrl;
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u32 syncfreq;
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u32 ccctlr;
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u32 bb_ctrl;
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u32 vinst_ctrl;
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u32 viiectlr;
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u32 vissctlr;
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u32 vipcssctlr;
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u8 seq_idx;
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u32 seq_ctrl[ETM_MAX_SEQ_STATES];
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u32 seq_rst;
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u32 seq_state;
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u8 cntr_idx;
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u32 cntrldvr[ETMv4_MAX_CNTR];
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u32 cntr_ctrl[ETMv4_MAX_CNTR];
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u32 cntr_val[ETMv4_MAX_CNTR];
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u8 res_idx;
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u32 res_ctrl[ETM_MAX_RES_SEL];
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u32 ss_ctrl[ETM_MAX_SS_CMP];
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u32 ss_status[ETM_MAX_SS_CMP];
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u32 ss_pe_cmp[ETM_MAX_SS_CMP];
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u8 addr_idx;
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u64 addr_val[ETM_MAX_SINGLE_ADDR_CMP];
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u64 addr_acc[ETM_MAX_SINGLE_ADDR_CMP];
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u8 addr_type[ETM_MAX_SINGLE_ADDR_CMP];
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u8 ctxid_idx;
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u64 ctxid_pid[ETMv4_MAX_CTXID_CMP];
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u32 ctxid_mask0;
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u32 ctxid_mask1;
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u8 vmid_idx;
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u64 vmid_val[ETM_MAX_VMID_CMP];
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u32 vmid_mask0;
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u32 vmid_mask1;
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u32 ext_inp;
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};
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/**
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* struct etm4_save_state - state to be preserved when ETM is without power
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*/
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struct etmv4_save_state {
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u32 trcprgctlr;
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u32 trcprocselr;
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u32 trcconfigr;
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u32 trcauxctlr;
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u32 trceventctl0r;
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u32 trceventctl1r;
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u32 trcstallctlr;
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u32 trctsctlr;
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u32 trcsyncpr;
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u32 trcccctlr;
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u32 trcbbctlr;
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u32 trctraceidr;
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u32 trcqctlr;
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u32 trcvictlr;
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u32 trcviiectlr;
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u32 trcvissctlr;
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u32 trcvipcssctlr;
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u32 trcvdctlr;
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u32 trcvdsacctlr;
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u32 trcvdarcctlr;
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u32 trcseqevr[ETM_MAX_SEQ_STATES];
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u32 trcseqrstevr;
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u32 trcseqstr;
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u32 trcextinselr;
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u32 trccntrldvr[ETMv4_MAX_CNTR];
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u32 trccntctlr[ETMv4_MAX_CNTR];
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u32 trccntvr[ETMv4_MAX_CNTR];
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u32 trcrsctlr[ETM_MAX_RES_SEL * 2];
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u32 trcssccr[ETM_MAX_SS_CMP];
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u32 trcsscsr[ETM_MAX_SS_CMP];
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u32 trcsspcicr[ETM_MAX_SS_CMP];
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u64 trcacvr[ETM_MAX_SINGLE_ADDR_CMP];
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u64 trcacatr[ETM_MAX_SINGLE_ADDR_CMP];
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u64 trccidcvr[ETMv4_MAX_CTXID_CMP];
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u64 trcvmidcvr[ETM_MAX_VMID_CMP];
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u32 trccidcctlr0;
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u32 trccidcctlr1;
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u32 trcvmidcctlr0;
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u32 trcvmidcctlr1;
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u32 trcclaimset;
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u32 cntr_val[ETMv4_MAX_CNTR];
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u32 seq_state;
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u32 vinst_ctrl;
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u32 ss_status[ETM_MAX_SS_CMP];
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u32 trcpdcr;
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};
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/**
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* struct etm4_drvdata - specifics associated to an ETM component
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* @base: Memory mapped base address for this component.
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* @dev: The device entity associated to this component.
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* @csdev: Component vitals needed by the framework.
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* @spinlock: Only one at a time pls.
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* @mode: This tracer's mode, i.e sysFS, Perf or disabled.
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* @cpu: The cpu this component is affined to.
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* @arch: ETM version number.
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* @nr_pe: The number of processing entity available for tracing.
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* @nr_pe_cmp: The number of processing entity comparator inputs that are
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* available for tracing.
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* @nr_addr_cmp:Number of pairs of address comparators available
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* as found in ETMIDR4 0-3.
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* @nr_cntr: Number of counters as found in ETMIDR5 bit 28-30.
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* @nr_ext_inp: Number of external input.
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* @numcidc: Number of contextID comparators.
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* @numvmidc: Number of VMID comparators.
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* @nrseqstate: The number of sequencer states that are implemented.
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* @nr_event: Indicates how many events the trace unit support.
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* @nr_resource:The number of resource selection pairs available for tracing.
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* @nr_ss_cmp: Number of single-shot comparator controls that are available.
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* @trcid: value of the current ID for this component.
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* @trcid_size: Indicates the trace ID width.
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* @ts_size: Global timestamp size field.
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* @ctxid_size: Size of the context ID field to consider.
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* @vmid_size: Size of the VM ID comparator to consider.
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* @ccsize: Indicates the size of the cycle counter in bits.
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* @ccitmin: minimum value that can be programmed in
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* @s_ex_level: In secure state, indicates whether instruction tracing is
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* supported for the corresponding Exception level.
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* @ns_ex_level:In non-secure state, indicates whether instruction tracing is
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* supported for the corresponding Exception level.
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* @sticky_enable: true if ETM base configuration has been done.
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* @boot_enable:True if we should start tracing at boot time.
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* @os_unlock: True if access to management registers is allowed.
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* @instrp0: Tracing of load and store instructions
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* as P0 elements is supported.
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* @trcbb: Indicates if the trace unit supports branch broadcast tracing.
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* @trccond: If the trace unit supports conditional
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* instruction tracing.
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* @retstack: Indicates if the implementation supports a return stack.
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* @trccci: Indicates if the trace unit supports cycle counting
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* for instruction.
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* @q_support: Q element support characteristics.
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* @trc_error: Whether a trace unit can trace a system
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* error exception.
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* @syncpr: Indicates if an implementation has a fixed
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* synchronization period.
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* @stall_ctrl: Enables trace unit functionality that prevents trace
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* unit buffer overflows.
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* @sysstall: Does the system support stall control of the PE?
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* @nooverflow: Indicate if overflow prevention is supported.
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* @atbtrig: If the implementation can support ATB triggers
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* @lpoverride: If the implementation can support low-power state over.
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* @config: structure holding configuration parameters.
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* @save_state: State to be preserved across power loss
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* @state_needs_restore: True when there is context to restore after PM exit
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*/
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struct etmv4_drvdata {
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void __iomem *base;
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struct device *dev;
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struct coresight_device *csdev;
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spinlock_t spinlock;
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local_t mode;
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int cpu;
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u8 arch;
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u8 nr_pe;
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u8 nr_pe_cmp;
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u8 nr_addr_cmp;
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u8 nr_cntr;
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u8 nr_ext_inp;
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u8 numcidc;
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u8 numvmidc;
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u8 nrseqstate;
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u8 nr_event;
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u8 nr_resource;
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u8 nr_ss_cmp;
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u8 trcid;
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u8 trcid_size;
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u8 ts_size;
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u8 ctxid_size;
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u8 vmid_size;
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u8 ccsize;
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u8 ccitmin;
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u8 s_ex_level;
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u8 ns_ex_level;
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u8 q_support;
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bool sticky_enable;
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bool boot_enable;
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bool os_unlock;
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bool instrp0;
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bool trcbb;
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bool trccond;
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bool retstack;
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bool trccci;
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bool trc_error;
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bool syncpr;
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bool stallctl;
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bool sysstall;
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bool nooverflow;
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bool atbtrig;
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bool lpoverride;
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struct etmv4_config config;
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struct etmv4_save_state *save_state;
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bool state_needs_restore;
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};
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/* Address comparator access types */
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enum etm_addr_acctype {
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ETM_INSTR_ADDR,
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ETM_DATA_LOAD_ADDR,
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ETM_DATA_STORE_ADDR,
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ETM_DATA_LOAD_STORE_ADDR,
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};
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/* Address comparator context types */
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enum etm_addr_ctxtype {
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ETM_CTX_NONE,
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ETM_CTX_CTXID,
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ETM_CTX_VMID,
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ETM_CTX_CTXID_VMID,
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};
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extern const struct attribute_group *coresight_etmv4_groups[];
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void etm4_config_trace_mode(struct etmv4_config *config);
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#endif
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