/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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/*
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* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
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*/
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#ifndef _UAPI__RK_PCIE_EP_H__
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#define _UAPI__RK_PCIE_EP_H__
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#include <linux/types.h>
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/* rkep device mode status definition */
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#define RKEP_MODE_BOOTROM 1
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#define RKEP_MODE_LOADER 2
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#define RKEP_MODE_KERNEL 3
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#define RKEP_MODE_FUN0 4
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/* Common status */
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#define RKEP_SMODE_INIT 0
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#define RKEP_SMODE_LNKRDY 1
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#define RKEP_SMODE_LNKUP 2
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#define RKEP_SMODE_ERR 0xff
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/* Firmware download status */
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#define RKEP_SMODE_FWDLRDY 0x10
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#define RKEP_SMODE_FWDLDONE 0x11
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/* Application status*/
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#define RKEP_SMODE_APPRDY 0x20
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/*
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* rockchip driver cache ioctrl input param
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*/
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struct pcie_ep_dma_cache_cfg {
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__u64 addr;
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__u32 size;
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};
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struct pcie_ep_dma_block {
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__u64 bus_paddr;
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__u64 local_paddr;
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__u32 size;
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};
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struct pcie_ep_dma_block_req {
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__u16 vir_id; /* Default 0 */
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__u8 chn;
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__u8 wr;
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__u32 flag;
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#define PCIE_EP_DMA_BLOCK_FLAG_COHERENT BIT(0) /* Cache coherent, 1-need, 0-None */
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struct pcie_ep_dma_block block;
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};
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#define PCIE_EP_OBJ_INFO_MAGIC 0x524B4550
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enum pcie_ep_obj_irq_type {
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OBJ_IRQ_UNKNOWN,
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OBJ_IRQ_DMA,
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OBJ_IRQ_USER,
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OBJ_IRQ_ELBI,
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};
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struct pcie_ep_obj_irq_dma_status {
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__u32 wr;
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__u32 rd;
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};
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enum pcie_ep_mmap_resource {
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PCIE_EP_MMAP_RESOURCE_DBI,
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PCIE_EP_MMAP_RESOURCE_BAR0,
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PCIE_EP_MMAP_RESOURCE_BAR2,
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PCIE_EP_MMAP_RESOURCE_BAR4,
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PCIE_EP_MMAP_RESOURCE_USER_MEM,
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PCIE_EP_MMAP_RESOURCE_RK3568_RC_DBI,
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PCIE_EP_MMAP_RESOURCE_RK3588_RC_DBI,
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PCIE_EP_MMAP_RESOURCE_MAX,
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};
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#define PCIE_EP_OBJ_INFO_MSI_DATA_NUM 0x8
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#define RKEP_EP_VIRTUAL_ID_MAX (PCIE_EP_OBJ_INFO_MSI_DATA_NUM * 32) /* 256 virtual_id */
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/*
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* rockchip ep device information which is store in BAR0
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*/
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struct pcie_ep_obj_info {
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__u32 magic;
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__u32 version;
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struct {
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__u16 mode;
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__u16 submode;
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} devmode;
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__u32 msi_data[PCIE_EP_OBJ_INFO_MSI_DATA_NUM];
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__u8 reserved[0x1D0];
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__u32 irq_type_rc; /* Generate in ep isr, valid only for rc, clear in rc */
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struct pcie_ep_obj_irq_dma_status dma_status_rc; /* Generate in ep isr, valid only for rc, clear in rc */
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__u32 irq_type_ep; /* Generate in ep isr, valid only for ep, clear in ep */
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struct pcie_ep_obj_irq_dma_status dma_status_ep; /* Generate in ep isr, valid only for ep, clear in ep */
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__u32 irq_user_data_rc; /* Generate in ep, valid only for rc, No need to clear */
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__u32 irq_user_data_ep; /* Generate in rc, valid only for ep, No need to clear */
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};
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/*
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* rockchip driver ep_obj poll ioctrl input param
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*/
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struct pcie_ep_obj_poll_virtual_id_cfg {
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__u32 timeout_ms;
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__u32 sync;
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__u32 virtual_id;
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__u32 poll_status;
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};
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#define PCIE_BASE 'P'
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#define PCIE_DMA_CACHE_INVALIDE _IOW(PCIE_BASE, 1, struct pcie_ep_dma_cache_cfg)
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#define PCIE_DMA_CACHE_FLUSH _IOW(PCIE_BASE, 2, struct pcie_ep_dma_cache_cfg)
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#define PCIE_DMA_IRQ_MASK_ALL _IOW(PCIE_BASE, 3, int)
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#define PCIE_EP_RAISE_MSI _IOW(PCIE_BASE, 4, int)
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#define PCIE_EP_SET_MMAP_RESOURCE _IOW(PCIE_BASE, 6, int)
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#define PCIE_EP_RAISE_ELBI _IOW(PCIE_BASE, 7, int)
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#define PCIE_EP_REQUEST_VIRTUAL_ID _IOR(PCIE_BASE, 16, int)
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#define PCIE_EP_RELEASE_VIRTUAL_ID _IOW(PCIE_BASE, 17, int)
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#define PCIE_EP_RAISE_IRQ_USER _IOW(PCIE_BASE, 18, int)
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#define PCIE_EP_POLL_IRQ_USER _IOW(PCIE_BASE, 19, struct pcie_ep_obj_poll_virtual_id_cfg)
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#define PCIE_EP_DMA_XFER_BLOCK _IOW(PCIE_BASE, 32, struct pcie_ep_dma_block_req)
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#endif
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