/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <malloc.h>
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#include <net.h>
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#include <netdev.h>
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#include <asm/cpm_8xx.h>
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#include <asm/io.h>
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#include <phy.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* define WANT_MII when MII support is required */
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#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY)
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#define WANT_MII
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#else
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#undef WANT_MII
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#endif
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#if defined(WANT_MII)
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#include <miiphy.h>
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#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
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#error "CONFIG_MII has to be defined!"
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#endif
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#endif
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#if defined(CONFIG_RMII) && !defined(WANT_MII)
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#error RMII support is unusable without a working PHY.
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#endif
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#ifdef CONFIG_SYS_DISCOVER_PHY
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static int mii_discover_phy(struct eth_device *dev);
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#endif
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int fec8xx_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg);
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int fec8xx_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
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u16 value);
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static struct ether_fcc_info_s
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{
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int ether_index;
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int fecp_offset;
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int phy_addr;
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int actual_phy_addr;
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int initialized;
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}
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ether_fcc_info[] = {
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#if defined(CONFIG_ETHER_ON_FEC1)
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{
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0,
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offsetof(immap_t, im_cpm.cp_fec1),
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CONFIG_FEC1_PHY,
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-1,
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0,
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},
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#endif
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#if defined(CONFIG_ETHER_ON_FEC2)
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{
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1,
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offsetof(immap_t, im_cpm.cp_fec2),
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CONFIG_FEC2_PHY,
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-1,
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0,
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},
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#endif
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};
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/* Ethernet Transmit and Receive Buffers */
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#define DBUF_LENGTH 1520
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#define TX_BUF_CNT 2
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#define TOUT_LOOP 100
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#define PKT_MAXBUF_SIZE 1518
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#define PKT_MINBUF_SIZE 64
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#define PKT_MAXBLR_SIZE 1520
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#ifdef __GNUC__
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static char txbuf[DBUF_LENGTH] __aligned(8);
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#else
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#error txbuf must be aligned.
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#endif
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static uint rxIdx; /* index of the current RX buffer */
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static uint txIdx; /* index of the current TX buffer */
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/*
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* FEC Ethernet Tx and Rx buffer descriptors allocated at the
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* immr->udata_bd address on Dual-Port RAM
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* Provide for Double Buffering
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*/
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struct common_buf_desc {
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cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
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cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
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};
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static struct common_buf_desc __iomem *rtx;
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static int fec_send(struct eth_device *dev, void *packet, int length);
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static int fec_recv(struct eth_device *dev);
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static int fec_init(struct eth_device *dev, bd_t *bd);
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static void fec_halt(struct eth_device *dev);
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#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
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static void __mii_init(void);
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#endif
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int fec_initialize(bd_t *bis)
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{
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struct eth_device *dev;
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struct ether_fcc_info_s *efis;
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int i;
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for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) {
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dev = malloc(sizeof(*dev));
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if (dev == NULL)
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hang();
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memset(dev, 0, sizeof(*dev));
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/* for FEC1 make sure that the name of the interface is the same
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as the old one for compatibility reasons */
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if (i == 0)
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strcpy(dev->name, "FEC");
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else
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sprintf(dev->name, "FEC%d",
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ether_fcc_info[i].ether_index + 1);
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efis = ðer_fcc_info[i];
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/*
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* reset actual phy addr
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*/
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efis->actual_phy_addr = -1;
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dev->priv = efis;
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dev->init = fec_init;
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dev->halt = fec_halt;
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dev->send = fec_send;
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dev->recv = fec_recv;
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eth_register(dev);
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#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
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int retval;
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struct mii_dev *mdiodev = mdio_alloc();
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if (!mdiodev)
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return -ENOMEM;
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strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
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mdiodev->read = fec8xx_miiphy_read;
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mdiodev->write = fec8xx_miiphy_write;
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retval = mdio_register(mdiodev);
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if (retval < 0)
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return retval;
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#endif
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}
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return 1;
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}
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static int fec_send(struct eth_device *dev, void *packet, int length)
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{
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int j, rc;
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struct ether_fcc_info_s *efis = dev->priv;
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fec_t __iomem *fecp =
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(fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
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/* section 16.9.23.3
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* Wait for ready
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*/
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j = 0;
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while ((in_be16(&rtx->txbd[txIdx].cbd_sc) & BD_ENET_TX_READY) &&
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(j < TOUT_LOOP)) {
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udelay(1);
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j++;
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}
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if (j >= TOUT_LOOP)
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printf("TX not ready\n");
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out_be32(&rtx->txbd[txIdx].cbd_bufaddr, (uint)packet);
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out_be16(&rtx->txbd[txIdx].cbd_datlen, length);
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setbits_be16(&rtx->txbd[txIdx].cbd_sc,
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BD_ENET_TX_READY | BD_ENET_TX_LAST);
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/* Activate transmit Buffer Descriptor polling */
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/* Descriptor polling active */
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out_be32(&fecp->fec_x_des_active, 0x01000000);
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j = 0;
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while ((in_be16(&rtx->txbd[txIdx].cbd_sc) & BD_ENET_TX_READY) &&
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(j < TOUT_LOOP)) {
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udelay(1);
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j++;
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}
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if (j >= TOUT_LOOP)
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printf("TX timeout\n");
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/* return only status bits */;
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rc = in_be16(&rtx->txbd[txIdx].cbd_sc) & BD_ENET_TX_STATS;
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txIdx = (txIdx + 1) % TX_BUF_CNT;
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return rc;
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}
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static int fec_recv(struct eth_device *dev)
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{
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struct ether_fcc_info_s *efis = dev->priv;
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fec_t __iomem *fecp =
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(fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
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int length;
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for (;;) {
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/* section 16.9.23.2 */
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if (in_be16(&rtx->rxbd[rxIdx].cbd_sc) & BD_ENET_RX_EMPTY) {
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length = -1;
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break; /* nothing received - leave for() loop */
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}
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length = in_be16(&rtx->rxbd[rxIdx].cbd_datlen);
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if (!(in_be16(&rtx->rxbd[rxIdx].cbd_sc) & 0x003f)) {
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uchar *rx = net_rx_packets[rxIdx];
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length -= 4;
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#if defined(CONFIG_CMD_CDP)
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if ((rx[0] & 1) != 0 &&
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memcmp((uchar *)rx, net_bcast_ethaddr, 6) != 0 &&
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!is_cdp_packet((uchar *)rx))
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rx = NULL;
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#endif
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/*
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* Pass the packet up to the protocol layers.
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*/
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if (rx != NULL)
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net_process_received_packet(rx, length);
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}
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/* Give the buffer back to the FEC. */
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out_be16(&rtx->rxbd[rxIdx].cbd_datlen, 0);
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/* wrap around buffer index when necessary */
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if ((rxIdx + 1) >= PKTBUFSRX) {
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out_be16(&rtx->rxbd[PKTBUFSRX - 1].cbd_sc,
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BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
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rxIdx = 0;
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} else {
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out_be16(&rtx->rxbd[rxIdx].cbd_sc, BD_ENET_RX_EMPTY);
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rxIdx++;
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}
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/* Try to fill Buffer Descriptors */
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/* Descriptor polling active */
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out_be32(&fecp->fec_r_des_active, 0x01000000);
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}
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return length;
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}
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/**************************************************************
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*
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* FEC Ethernet Initialization Routine
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*
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*************************************************************/
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#define FEC_ECNTRL_PINMUX 0x00000004
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#define FEC_ECNTRL_ETHER_EN 0x00000002
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#define FEC_ECNTRL_RESET 0x00000001
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#define FEC_RCNTRL_BC_REJ 0x00000010
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#define FEC_RCNTRL_PROM 0x00000008
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#define FEC_RCNTRL_MII_MODE 0x00000004
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#define FEC_RCNTRL_DRT 0x00000002
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#define FEC_RCNTRL_LOOP 0x00000001
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#define FEC_TCNTRL_FDEN 0x00000004
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#define FEC_TCNTRL_HBC 0x00000002
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#define FEC_TCNTRL_GTS 0x00000001
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#define FEC_RESET_DELAY 50
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#if defined(CONFIG_RMII)
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static inline void fec_10Mbps(struct eth_device *dev)
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{
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struct ether_fcc_info_s *efis = dev->priv;
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int fecidx = efis->ether_index;
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uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
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immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
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if ((unsigned int)fecidx >= 2)
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hang();
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setbits_be32(&immr->im_cpm.cp_cptr, mask);
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}
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static inline void fec_100Mbps(struct eth_device *dev)
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{
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struct ether_fcc_info_s *efis = dev->priv;
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int fecidx = efis->ether_index;
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uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
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immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
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if ((unsigned int)fecidx >= 2)
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hang();
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clrbits_be32(&immr->im_cpm.cp_cptr, mask);
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}
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#endif
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static inline void fec_full_duplex(struct eth_device *dev)
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{
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struct ether_fcc_info_s *efis = dev->priv;
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fec_t __iomem *fecp =
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(fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
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clrbits_be32(&fecp->fec_r_cntrl, FEC_RCNTRL_DRT);
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setbits_be32(&fecp->fec_x_cntrl, FEC_TCNTRL_FDEN); /* FD enable */
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}
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static inline void fec_half_duplex(struct eth_device *dev)
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{
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struct ether_fcc_info_s *efis = dev->priv;
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fec_t __iomem *fecp =
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(fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
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setbits_be32(&fecp->fec_r_cntrl, FEC_RCNTRL_DRT);
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clrbits_be32(&fecp->fec_x_cntrl, FEC_TCNTRL_FDEN); /* FD disable */
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}
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static void fec_pin_init(int fecidx)
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{
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bd_t *bd = gd->bd;
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immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
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/*
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* Set MII speed to 2.5 MHz or slightly below.
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*
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* According to the MPC860T (Rev. D) Fast ethernet controller user
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* manual (6.2.14),
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* the MII management interface clock must be less than or equal
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* to 2.5 MHz.
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* This MDC frequency is equal to system clock / (2 * MII_SPEED).
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* Then MII_SPEED = system_clock / 2 * 2,5 MHz.
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*
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* All MII configuration is done via FEC1 registers:
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*/
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out_be32(&immr->im_cpm.cp_fec1.fec_mii_speed,
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((bd->bi_intfreq + 4999999) / 5000000) << 1);
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#if defined(CONFIG_MPC885) && defined(WANT_MII)
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/* use MDC for MII */
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setbits_be16(&immr->im_ioport.iop_pdpar, 0x0080);
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clrbits_be16(&immr->im_ioport.iop_pddir, 0x0080);
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#endif
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if (fecidx == 0) {
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#if defined(CONFIG_ETHER_ON_FEC1)
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#if defined(CONFIG_MPC885) /* MPC87x/88x have got 2 FECs and different pinout */
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#if !defined(CONFIG_RMII)
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setbits_be16(&immr->im_ioport.iop_papar, 0xf830);
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setbits_be16(&immr->im_ioport.iop_padir, 0x0830);
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clrbits_be16(&immr->im_ioport.iop_padir, 0xf000);
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setbits_be32(&immr->im_cpm.cp_pbpar, 0x00001001);
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clrbits_be32(&immr->im_cpm.cp_pbdir, 0x00001001);
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setbits_be16(&immr->im_ioport.iop_pcpar, 0x000c);
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clrbits_be16(&immr->im_ioport.iop_pcdir, 0x000c);
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setbits_be32(&immr->im_cpm.cp_pepar, 0x00000003);
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setbits_be32(&immr->im_cpm.cp_pedir, 0x00000003);
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clrbits_be32(&immr->im_cpm.cp_peso, 0x00000003);
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clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000100);
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#else
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#if !defined(CONFIG_FEC1_PHY_NORXERR)
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setbits_be16(&immr->im_ioport.iop_papar, 0x1000);
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clrbits_be16(&immr->im_ioport.iop_padir, 0x1000);
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#endif
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setbits_be16(&immr->im_ioport.iop_papar, 0xe810);
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setbits_be16(&immr->im_ioport.iop_padir, 0x0810);
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clrbits_be16(&immr->im_ioport.iop_padir, 0xe000);
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setbits_be32(&immr->im_cpm.cp_pbpar, 0x00000001);
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clrbits_be32(&immr->im_cpm.cp_pbdir, 0x00000001);
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setbits_be32(&immr->im_cpm.cp_cptr, 0x00000100);
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clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000050);
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#endif /* !CONFIG_RMII */
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#else
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/*
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* Configure all of port D for MII.
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*/
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out_be16(&immr->im_ioport.iop_pdpar, 0x1fff);
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out_be16(&immr->im_ioport.iop_pddir, 0x1fff);
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#if defined(CONFIG_TARGET_MCR3000)
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out_be16(&immr->im_ioport.iop_papar, 0xBBFF);
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out_be16(&immr->im_ioport.iop_padir, 0x04F0);
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out_be16(&immr->im_ioport.iop_paodr, 0x0000);
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out_be32(&immr->im_cpm.cp_pbpar, 0x000133FF);
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out_be32(&immr->im_cpm.cp_pbdir, 0x0003BF0F);
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out_be16(&immr->im_cpm.cp_pbodr, 0x0000);
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out_be16(&immr->im_ioport.iop_pcpar, 0x0400);
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out_be16(&immr->im_ioport.iop_pcdir, 0x0080);
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out_be16(&immr->im_ioport.iop_pcso , 0x0D53);
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out_be16(&immr->im_ioport.iop_pcint, 0x0000);
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out_be16(&immr->im_ioport.iop_pdpar, 0x03FE);
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out_be16(&immr->im_ioport.iop_pddir, 0x1C09);
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setbits_be32(&immr->im_ioport.utmode, 0x80);
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#endif
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#endif
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#endif /* CONFIG_ETHER_ON_FEC1 */
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} else if (fecidx == 1) {
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#if defined(CONFIG_ETHER_ON_FEC2)
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#if defined(CONFIG_MPC885) /* MPC87x/88x have got 2 FECs and different pinout */
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#if !defined(CONFIG_RMII)
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setbits_be32(&immr->im_cpm.cp_pepar, 0x0003fffc);
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setbits_be32(&immr->im_cpm.cp_pedir, 0x0003fffc);
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clrbits_be32(&immr->im_cpm.cp_peso, 0x000087fc);
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setbits_be32(&immr->im_cpm.cp_peso, 0x00037800);
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clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000080);
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#else
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#if !defined(CONFIG_FEC2_PHY_NORXERR)
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setbits_be32(&immr->im_cpm.cp_pepar, 0x00000010);
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setbits_be32(&immr->im_cpm.cp_pedir, 0x00000010);
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clrbits_be32(&immr->im_cpm.cp_peso, 0x00000010);
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#endif
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setbits_be32(&immr->im_cpm.cp_pepar, 0x00039620);
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setbits_be32(&immr->im_cpm.cp_pedir, 0x00039620);
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setbits_be32(&immr->im_cpm.cp_peso, 0x00031000);
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clrbits_be32(&immr->im_cpm.cp_peso, 0x00008620);
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setbits_be32(&immr->im_cpm.cp_cptr, 0x00000080);
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clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000028);
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#endif /* CONFIG_RMII */
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#endif /* CONFIG_MPC885 */
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#endif /* CONFIG_ETHER_ON_FEC2 */
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}
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}
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static int fec_reset(fec_t __iomem *fecp)
|
{
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int i;
|
|
/* Whack a reset.
|
* A delay is required between a reset of the FEC block and
|
* initialization of other FEC registers because the reset takes
|
* some time to complete. If you don't delay, subsequent writes
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* to FEC registers might get killed by the reset routine which is
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* still in progress.
|
*/
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out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);
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for (i = 0; (in_be32(&fecp->fec_ecntrl) & FEC_ECNTRL_RESET) &&
|
(i < FEC_RESET_DELAY); ++i)
|
udelay(1);
|
|
if (i == FEC_RESET_DELAY)
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return -1;
|
|
return 0;
|
}
|
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static int fec_init(struct eth_device *dev, bd_t *bd)
|
{
|
struct ether_fcc_info_s *efis = dev->priv;
|
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
|
fec_t __iomem *fecp =
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(fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
|
int i;
|
|
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
|
/* the MII interface is connected to FEC1
|
* so for the miiphy_xxx function to work we must
|
* call mii_init since fec_halt messes the thing up
|
*/
|
if (efis->ether_index != 0)
|
__mii_init();
|
#endif
|
|
if (fec_reset(fecp) < 0)
|
printf("FEC_RESET_DELAY timeout\n");
|
|
/* We use strictly polling mode only
|
*/
|
out_be32(&fecp->fec_imask, 0);
|
|
/* Clear any pending interrupt
|
*/
|
out_be32(&fecp->fec_ievent, 0xffc0);
|
|
/* No need to set the IVEC register */
|
|
/* Set station address
|
*/
|
#define ea dev->enetaddr
|
out_be32(&fecp->fec_addr_low, (ea[0] << 24) | (ea[1] << 16) |
|
(ea[2] << 8) | ea[3]);
|
out_be16(&fecp->fec_addr_high, (ea[4] << 8) | ea[5]);
|
#undef ea
|
|
#if defined(CONFIG_CMD_CDP)
|
/*
|
* Turn on multicast address hash table
|
*/
|
out_be32(&fecp->fec_hash_table_high, 0xffffffff);
|
out_be32(&fecp->fec_hash_table_low, 0xffffffff);
|
#else
|
/* Clear multicast address hash table
|
*/
|
out_be32(&fecp->fec_hash_table_high, 0);
|
out_be32(&fecp->fec_hash_table_low, 0);
|
#endif
|
|
/* Set maximum receive buffer size.
|
*/
|
out_be32(&fecp->fec_r_buff_size, PKT_MAXBLR_SIZE);
|
|
/* Set maximum frame length
|
*/
|
out_be32(&fecp->fec_r_hash, PKT_MAXBUF_SIZE);
|
|
/*
|
* Setup Buffers and Buffer Descriptors
|
*/
|
rxIdx = 0;
|
txIdx = 0;
|
|
if (!rtx)
|
rtx = (struct common_buf_desc __iomem *)
|
(immr->im_cpm.cp_dpmem + CPM_FEC_BASE);
|
/*
|
* Setup Receiver Buffer Descriptors (13.14.24.18)
|
* Settings:
|
* Empty, Wrap
|
*/
|
for (i = 0; i < PKTBUFSRX; i++) {
|
out_be16(&rtx->rxbd[i].cbd_sc, BD_ENET_RX_EMPTY);
|
out_be16(&rtx->rxbd[i].cbd_datlen, 0); /* Reset */
|
out_be32(&rtx->rxbd[i].cbd_bufaddr, (uint)net_rx_packets[i]);
|
}
|
setbits_be16(&rtx->rxbd[PKTBUFSRX - 1].cbd_sc, BD_ENET_RX_WRAP);
|
|
/*
|
* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
|
* Settings:
|
* Last, Tx CRC
|
*/
|
for (i = 0; i < TX_BUF_CNT; i++) {
|
out_be16(&rtx->txbd[i].cbd_sc, BD_ENET_TX_LAST | BD_ENET_TX_TC);
|
out_be16(&rtx->txbd[i].cbd_datlen, 0); /* Reset */
|
out_be32(&rtx->txbd[i].cbd_bufaddr, (uint)txbuf);
|
}
|
setbits_be16(&rtx->txbd[TX_BUF_CNT - 1].cbd_sc, BD_ENET_TX_WRAP);
|
|
/* Set receive and transmit descriptor base
|
*/
|
out_be32(&fecp->fec_r_des_start, (__force unsigned int)rtx->rxbd);
|
out_be32(&fecp->fec_x_des_start, (__force unsigned int)rtx->txbd);
|
|
/* Enable MII mode
|
*/
|
/* Half duplex mode */
|
out_be32(&fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT);
|
out_be32(&fecp->fec_x_cntrl, 0);
|
|
/* Enable big endian and don't care about SDMA FC.
|
*/
|
out_be32(&fecp->fec_fun_code, 0x78000000);
|
|
/*
|
* Setup the pin configuration of the FEC
|
*/
|
fec_pin_init(efis->ether_index);
|
|
rxIdx = 0;
|
txIdx = 0;
|
|
/*
|
* Now enable the transmit and receive processing
|
*/
|
out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
|
|
if (efis->phy_addr == -1) {
|
#ifdef CONFIG_SYS_DISCOVER_PHY
|
/*
|
* wait for the PHY to wake up after reset
|
*/
|
efis->actual_phy_addr = mii_discover_phy(dev);
|
|
if (efis->actual_phy_addr == -1) {
|
printf("Unable to discover phy!\n");
|
return -1;
|
}
|
#else
|
efis->actual_phy_addr = -1;
|
#endif
|
} else {
|
efis->actual_phy_addr = efis->phy_addr;
|
}
|
|
#if defined(CONFIG_MII) && defined(CONFIG_RMII)
|
/*
|
* adapt the RMII speed to the speed of the phy
|
*/
|
if (miiphy_speed(dev->name, efis->actual_phy_addr) == _100BASET)
|
fec_100Mbps(dev);
|
else
|
fec_10Mbps(dev);
|
#endif
|
|
#if defined(CONFIG_MII)
|
/*
|
* adapt to the half/full speed settings
|
*/
|
if (miiphy_duplex(dev->name, efis->actual_phy_addr) == FULL)
|
fec_full_duplex(dev);
|
else
|
fec_half_duplex(dev);
|
#endif
|
|
/* And last, try to fill Rx Buffer Descriptors */
|
/* Descriptor polling active */
|
out_be32(&fecp->fec_r_des_active, 0x01000000);
|
|
efis->initialized = 1;
|
|
return 0;
|
}
|
|
|
static void fec_halt(struct eth_device *dev)
|
{
|
struct ether_fcc_info_s *efis = dev->priv;
|
fec_t __iomem *fecp =
|
(fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
|
int i;
|
|
/* avoid halt if initialized; mii gets stuck otherwise */
|
if (!efis->initialized)
|
return;
|
|
/* Whack a reset.
|
* A delay is required between a reset of the FEC block and
|
* initialization of other FEC registers because the reset takes
|
* some time to complete. If you don't delay, subsequent writes
|
* to FEC registers might get killed by the reset routine which is
|
* still in progress.
|
*/
|
|
out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);
|
for (i = 0; (in_be32(&fecp->fec_ecntrl) & FEC_ECNTRL_RESET) &&
|
(i < FEC_RESET_DELAY); ++i)
|
udelay(1);
|
|
if (i == FEC_RESET_DELAY) {
|
printf("FEC_RESET_DELAY timeout\n");
|
return;
|
}
|
|
efis->initialized = 0;
|
}
|
|
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
|
|
/* Make MII read/write commands for the FEC.
|
*/
|
|
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \
|
(REG & 0x1f) << 18))
|
|
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \
|
(REG & 0x1f) << 18) | \
|
(VAL & 0xffff))
|
|
/* Interrupt events/masks.
|
*/
|
#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
|
#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
|
#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
|
#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
|
#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
|
#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
|
#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
|
#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
|
#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
|
#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
|
|
/* send command to phy using mii, wait for result */
|
static uint
|
mii_send(uint mii_cmd)
|
{
|
uint mii_reply;
|
fec_t __iomem *ep;
|
int cnt;
|
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
|
|
ep = &immr->im_cpm.cp_fec;
|
|
out_be32(&ep->fec_mii_data, mii_cmd); /* command to phy */
|
|
/* wait for mii complete */
|
cnt = 0;
|
while (!(in_be32(&ep->fec_ievent) & FEC_ENET_MII)) {
|
if (++cnt > 1000) {
|
printf("mii_send STUCK!\n");
|
break;
|
}
|
}
|
mii_reply = in_be32(&ep->fec_mii_data); /* result from phy */
|
out_be32(&ep->fec_ievent, FEC_ENET_MII); /* clear MII complete */
|
return mii_reply & 0xffff; /* data read from phy */
|
}
|
#endif
|
|
#if defined(CONFIG_SYS_DISCOVER_PHY)
|
static int mii_discover_phy(struct eth_device *dev)
|
{
|
#define MAX_PHY_PASSES 11
|
uint phyno;
|
int pass;
|
uint phytype;
|
int phyaddr;
|
|
phyaddr = -1; /* didn't find a PHY yet */
|
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
if (pass > 1) {
|
/* PHY may need more time to recover from reset.
|
* The LXT970 needs 50ms typical, no maximum is
|
* specified, so wait 10ms before try again.
|
* With 11 passes this gives it 100ms to wake up.
|
*/
|
udelay(10000); /* wait 10ms */
|
}
|
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
|
phytype = mii_send(mk_mii_read(phyno, MII_PHYSID2));
|
if (phytype != 0xffff) {
|
phyaddr = phyno;
|
phytype |= mii_send(mk_mii_read(phyno,
|
MII_PHYSID1)) << 16;
|
}
|
}
|
}
|
if (phyaddr < 0)
|
printf("No PHY device found.\n");
|
|
return phyaddr;
|
}
|
#endif /* CONFIG_SYS_DISCOVER_PHY */
|
|
#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && !defined(CONFIG_BITBANGMII)
|
|
/****************************************************************************
|
* mii_init -- Initialize the MII via FEC 1 for MII command without ethernet
|
* This function is a subset of eth_init
|
****************************************************************************
|
*/
|
static void __mii_init(void)
|
{
|
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
|
fec_t __iomem *fecp = &immr->im_cpm.cp_fec;
|
|
if (fec_reset(fecp) < 0)
|
printf("FEC_RESET_DELAY timeout\n");
|
|
/* We use strictly polling mode only
|
*/
|
out_be32(&fecp->fec_imask, 0);
|
|
/* Clear any pending interrupt
|
*/
|
out_be32(&fecp->fec_ievent, 0xffc0);
|
|
/* Now enable the transmit and receive processing
|
*/
|
out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
|
}
|
|
void mii_init(void)
|
{
|
int i;
|
|
__mii_init();
|
|
/* Setup the pin configuration of the FEC(s)
|
*/
|
for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++)
|
fec_pin_init(ether_fcc_info[i].ether_index);
|
}
|
|
/*****************************************************************************
|
* Read and write a MII PHY register, routines used by MII Utilities
|
*
|
* FIXME: These routines are expected to return 0 on success, but mii_send
|
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
* no PHY connected...
|
* For now always return 0.
|
* FIXME: These routines only work after calling eth_init() at least once!
|
* Otherwise they hang in mii_send() !!! Sorry!
|
*****************************************************************************/
|
|
int fec8xx_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg)
|
{
|
unsigned short value = 0;
|
short rdreg; /* register working value */
|
|
rdreg = mii_send(mk_mii_read(addr, reg));
|
|
value = rdreg;
|
return value;
|
}
|
|
int fec8xx_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
|
u16 value)
|
{
|
(void)mii_send(mk_mii_write(addr, reg, value));
|
|
return 0;
|
}
|
#endif
|
