/*
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* Altera 10/100/1000 triple speed ethernet mac
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*
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* Copyright (C) 2008 Altera Corporation.
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* Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _ALTERA_TSE_H_
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#define _ALTERA_TSE_H_
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#define __packed_1_ __packed __aligned(1)
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/* dma type */
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#define ALT_SGDMA 0
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#define ALT_MSGDMA 1
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/* SGDMA Stuff */
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#define ALT_SGDMA_STATUS_BUSY_MSK BIT(4)
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#define ALT_SGDMA_CONTROL_RUN_MSK BIT(5)
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#define ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK BIT(6)
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#define ALT_SGDMA_CONTROL_SOFTWARERESET_MSK BIT(16)
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/*
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* Descriptor control bit masks & offsets
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*
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* Note: The control byte physically occupies bits [31:24] in memory.
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* The following bit-offsets are expressed relative to the LSB of
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* the control register bitfield.
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*/
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#define ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK BIT(0)
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#define ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK BIT(1)
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#define ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK BIT(2)
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#define ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK BIT(7)
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/*
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* Descriptor status bit masks & offsets
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*
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* Note: The status byte physically occupies bits [23:16] in memory.
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* The following bit-offsets are expressed relative to the LSB of
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* the status register bitfield.
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*/
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#define ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK BIT(7)
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/*
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* The SGDMA controller buffer descriptor allocates
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* 64 bits for each address. To support ANSI C, the
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* struct implementing a descriptor places 32-bits
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* of padding directly above each address; each pad must
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* be cleared when initializing a descriptor.
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*/
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/*
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* Buffer Descriptor data structure
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*
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*/
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struct alt_sgdma_descriptor {
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u32 source; /* the address of data to be read. */
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u32 source_pad;
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u32 destination; /* the address to write data */
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u32 destination_pad;
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u32 next; /* the next descriptor in the list. */
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u32 next_pad;
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u16 bytes_to_transfer; /* the number of bytes to transfer */
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u8 read_burst;
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u8 write_burst;
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u16 actual_bytes_transferred;/* bytes transferred by DMA */
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u8 descriptor_status;
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u8 descriptor_control;
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} __packed_1_;
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/* SG-DMA Control/Status Slave registers map */
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struct alt_sgdma_registers {
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u32 status;
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u32 status_pad[3];
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u32 control;
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u32 control_pad[3];
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u32 next_descriptor_pointer;
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u32 descriptor_pad[3];
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};
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/* mSGDMA Stuff */
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/* mSGDMA extended descriptor format */
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struct msgdma_extended_desc {
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u32 read_addr_lo; /* data buffer source address low bits */
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u32 write_addr_lo; /* data buffer destination address low bits */
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u32 len;
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u32 burst_seq_num;
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u32 stride;
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u32 read_addr_hi; /* data buffer source address high bits */
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u32 write_addr_hi; /* data buffer destination address high bits */
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u32 control; /* characteristics of the transfer */
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};
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/* mSGDMA descriptor control field bit definitions */
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#define MSGDMA_DESC_CTL_GEN_SOP BIT(8)
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#define MSGDMA_DESC_CTL_GEN_EOP BIT(9)
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#define MSGDMA_DESC_CTL_END_ON_EOP BIT(12)
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#define MSGDMA_DESC_CTL_END_ON_LEN BIT(13)
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#define MSGDMA_DESC_CTL_GO BIT(31)
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/* Tx buffer control flags */
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#define MSGDMA_DESC_CTL_TX_SINGLE (MSGDMA_DESC_CTL_GEN_SOP | \
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MSGDMA_DESC_CTL_GEN_EOP | \
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MSGDMA_DESC_CTL_GO)
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#define MSGDMA_DESC_CTL_RX_SINGLE (MSGDMA_DESC_CTL_END_ON_EOP | \
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MSGDMA_DESC_CTL_END_ON_LEN | \
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MSGDMA_DESC_CTL_GO)
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/* mSGDMA extended descriptor stride definitions */
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#define MSGDMA_DESC_TX_STRIDE 0x00010001
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#define MSGDMA_DESC_RX_STRIDE 0x00010001
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/* mSGDMA dispatcher control and status register map */
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struct msgdma_csr {
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u32 status; /* Read/Clear */
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u32 control; /* Read/Write */
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u32 rw_fill_level;
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u32 resp_fill_level; /* bit 15:0 */
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u32 rw_seq_num;
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u32 pad[3]; /* reserved */
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};
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/* mSGDMA CSR status register bit definitions */
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#define MSGDMA_CSR_STAT_BUSY BIT(0)
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#define MSGDMA_CSR_STAT_RESETTING BIT(6)
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#define MSGDMA_CSR_STAT_MASK 0x3FF
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/* mSGDMA CSR control register bit definitions */
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#define MSGDMA_CSR_CTL_RESET BIT(1)
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/* mSGDMA response register map */
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struct msgdma_response {
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u32 bytes_transferred;
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u32 status;
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};
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/* TSE Stuff */
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#define ALTERA_TSE_CMD_TX_ENA_MSK BIT(0)
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#define ALTERA_TSE_CMD_RX_ENA_MSK BIT(1)
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#define ALTERA_TSE_CMD_ETH_SPEED_MSK BIT(3)
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#define ALTERA_TSE_CMD_HD_ENA_MSK BIT(10)
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#define ALTERA_TSE_CMD_SW_RESET_MSK BIT(13)
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#define ALTERA_TSE_CMD_ENA_10_MSK BIT(25)
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#define ALT_TSE_SW_RESET_TIMEOUT (3 * CONFIG_SYS_HZ)
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#define ALT_TSE_SGDMA_BUSY_TIMEOUT (3 * CONFIG_SYS_HZ)
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/* MAC register Space */
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struct alt_tse_mac {
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u32 megacore_revision;
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u32 scratch_pad;
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u32 command_config;
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u32 mac_addr_0;
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u32 mac_addr_1;
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u32 max_frame_length;
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u32 pause_quanta;
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u32 rx_sel_empty_threshold;
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u32 rx_sel_full_threshold;
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u32 tx_sel_empty_threshold;
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u32 tx_sel_full_threshold;
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u32 rx_almost_empty_threshold;
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u32 rx_almost_full_threshold;
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u32 tx_almost_empty_threshold;
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u32 tx_almost_full_threshold;
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u32 mdio_phy0_addr;
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u32 mdio_phy1_addr;
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u32 reserved1[0x29];
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/*FIFO control register. */
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u32 tx_cmd_stat;
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u32 rx_cmd_stat;
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u32 reserved2[0x44];
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/*Registers 0 to 31 within PHY device 0/1 */
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u32 mdio_phy0[0x20];
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u32 mdio_phy1[0x20];
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/*4 Supplemental MAC Addresses */
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u32 supp_mac_addr_0_0;
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u32 supp_mac_addr_0_1;
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u32 supp_mac_addr_1_0;
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u32 supp_mac_addr_1_1;
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u32 supp_mac_addr_2_0;
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u32 supp_mac_addr_2_1;
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u32 supp_mac_addr_3_0;
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u32 supp_mac_addr_3_1;
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u32 reserved3[0x38];
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};
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struct tse_ops {
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int (*send)(struct udevice *dev, void *packet, int length);
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int (*recv)(struct udevice *dev, int flags, uchar **packetp);
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int (*free_pkt)(struct udevice *dev, uchar *packet, int length);
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void (*stop)(struct udevice *dev);
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};
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struct altera_tse_priv {
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struct alt_tse_mac *mac_dev;
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void *sgdma_rx;
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void *sgdma_tx;
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unsigned int rx_fifo_depth;
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unsigned int tx_fifo_depth;
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void *rx_desc;
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void *tx_desc;
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void *rx_resp;
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unsigned char *rx_buf;
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unsigned int phyaddr;
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unsigned int interface;
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struct phy_device *phydev;
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struct mii_dev *bus;
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const struct tse_ops *ops;
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int dma_type;
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};
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#endif /* _ALTERA_TSE_H_ */
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