Lightweight UBI and UBI fastmap support
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# Copyright (C) Thomas Gleixner <tglx@linutronix.de>
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#
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# SPDX-License-Identifier: GPL 2.0+ BSD-3-Clause
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Scans the UBI information and loads the requested static volumes into
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memory.
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Configuration Options:
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CONFIG_SPL_UBI
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Enables the SPL UBI support
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CONFIG_SPL_UBI_MAX_VOL_LEBS
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The maximum number of logical eraseblocks which a static volume
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to load can contain. Used for sizing the scan data structure
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CONFIG_SPL_UBI_MAX_PEB_SIZE
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The maximum physical erase block size. Either a compile time
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constant or runtime detection. Used for sizing the scan data
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structure
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CONFIG_SPL_UBI_MAX_PEBS
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The maximum physical erase block count. Either a compile time
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constant or runtime detection. Used for sizing the scan data
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structure
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CONFIG_SPL_UBI_VOL_IDS
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The maximum volume ids which can be loaded. Used for sizing the
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scan data structure.
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Usage notes:
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In the board config file define for example:
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#define CONFIG_SPL_UBI
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#define CONFIG_SPL_UBI_MAX_VOL_LEBS 256
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#define CONFIG_SPL_UBI_MAX_PEB_SIZE (256*1024)
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#define CONFIG_SPL_UBI_MAX_PEBS 4096
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#define CONFIG_SPL_UBI_VOL_IDS 8
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The size requirement is roughly as follows:
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2k for the basic data structure
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+ CONFIG_SPL_UBI_VOL_IDS * CONFIG_SPL_UBI_MAX_VOL_LEBS * 8
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+ CONFIG_SPL_UBI_MAX_PEBS * 64
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+ CONFIG_SPL_UBI_MAX_PEB_SIZE * UBI_FM_MAX_BLOCKS
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The last one is big, but I really don't care in that stage. Real world
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implementations only use the first couple of blocks, but the code
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handles up to UBI_FM_MAX_BLOCKS.
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Given the above configuration example the requirement is about 5M
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which is usually not a problem to reserve in the RAM along with the
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other areas like the kernel/dts load address.
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So something like this will do the trick:
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#define SPL_FINFO_ADDR 0x80800000
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#define SPL_DTB_LOAD_ADDR 0x81800000
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#define SPL_KERNEL_LOAD_ADDR 0x82000000
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In the board file, implement the following:
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static struct ubispl_load myvolumes[] = {
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{
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.vol_id = 0, /* kernel volume */
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.load_addr = (void *)SPL_KERNEL_LOAD_ADDR,
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},
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{
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.vol_id = 1, /* DT blob */
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.load_addr = (void *)SPL_DTB_LOAD_ADDR,
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}
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};
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int spl_start_uboot(void)
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{
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struct ubispl_info info;
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info.ubi = (struct ubi_scan_info *) SPL_FINFO_ADDR;
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info.fastmap = 1;
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info.read = nand_spl_read_flash;
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#if COMPILE_TIME_DEFINED
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/*
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* MY_NAND_NR_SPL_PEBS is the number of physical erase blocks
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* in the FLASH which are reserved for the SPL. Think about
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* mtd partitions:
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*
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* part_spl { .start = 0, .end = 4 }
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* part_ubi { .start = 4, .end = NR_PEBS }
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*/
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info.peb_offset = MY_NAND_NR_SPL_PEBS;
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info.peb_size = CONFIG_SYS_NAND_BLOCK_SIZE;
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info.vid_offset = MY_NAND_UBI_VID_OFFS;
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info.leb_start = MY_NAND_UBI_DATA_OFFS;
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info.peb_count = MY_NAND_UBI_NUM_PEBS;
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#else
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get_flash_info(&flash_info);
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info.peb_offset = MY_NAND_NR_SPL_PEBS;
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info.peb_size = flash_info.peb_size;
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/*
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* The VID and Data offset depend on the capability of the
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* FLASH chip to do subpage writes.
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*
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* If the flash chip supports subpage writes, then the VID
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* header starts at the second subpage. So for 2k pages size
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* with 4 subpages the VID offset is 512. The DATA offset is 2k.
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*
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* If the flash chip does not support subpage writes then the
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* VID offset is FLASH_PAGE_SIZE and the DATA offset
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* 2 * FLASH_PAGE_SIZE
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*/
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info.vid_offset = flash_info.vid_offset;
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info.leb_start = flash_info.data_offset;
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/*
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* The flash reports the total number of erase blocks, so
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* we need to subtract the number of blocks which are reserved
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* for the SPL itself and not managed by UBI.
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*/
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info.peb_count = flash_info.peb_count - MY_NAND_NR_SPL_PEBS;
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#endif
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ret = ubispl_load_volumes(&info, myvolumes, ARRAY_SIZE(myvolumes);
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....
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}
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Note: you can load any payload that way. You can even load u-boot from
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UBI, so the only non UBI managed FLASH area is the one which is
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reserved for the SPL itself and read from the SoC ROM.
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And you can do fallback scenarios:
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if (ubispl_load_volumes(&info, volumes0, ARRAY_SIZE(volumes0)))
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if (ubispl_load_volumes(&info, volumes1, ARRAY_SIZE(volumes1)))
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ubispl_load_volumes(&info, vol_uboot, ARRAY_SIZE(vol_uboot));
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