/*
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* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/addrspace.h>
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#include <asm/types.h>
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#include <mach/ar71xx_regs.h>
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#include <mach/ath79.h>
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DECLARE_GLOBAL_DATA_PTR;
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static u32 ar933x_get_xtal(void)
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{
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u32 val;
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val = ath79_get_bootstrap();
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if (val & AR933X_BOOTSTRAP_REF_CLK_40)
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return 40000000;
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else
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return 25000000;
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}
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int get_serial_clock(void)
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{
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return ar933x_get_xtal();
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}
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int get_clocks(void)
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{
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void __iomem *regs;
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u32 val, xtal, pll, div;
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regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
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MAP_NOCACHE);
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xtal = ar933x_get_xtal();
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val = readl(regs + AR933X_PLL_CPU_CONFIG_REG);
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/* VCOOUT = XTAL * DIV_INT */
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div = (val >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT)
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& AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
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pll = xtal / div;
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/* PLLOUT = VCOOUT * (1/2^OUTDIV) */
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div = (val >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT)
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& AR933X_PLL_CPU_CONFIG_NINT_MASK;
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pll *= div;
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div = (val >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT)
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& AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
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if (!div)
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div = 1;
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pll >>= div;
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val = readl(regs + AR933X_PLL_CLK_CTRL_REG);
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/* CPU_CLK = PLLOUT / CPU_POST_DIV */
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div = ((val >> AR933X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT)
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& AR933X_PLL_CLK_CTRL_CPU_POST_DIV_MASK) + 1;
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gd->cpu_clk = pll / div;
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/* DDR_CLK = PLLOUT / DDR_POST_DIV */
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div = ((val >> AR933X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT)
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& AR933X_PLL_CLK_CTRL_DDR_POST_DIV_MASK) + 1;
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gd->mem_clk = pll / div;
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/* AHB_CLK = PLLOUT / AHB_POST_DIV */
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div = ((val >> AR933X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT)
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& AR933X_PLL_CLK_CTRL_AHB_POST_DIV_MASK) + 1;
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gd->bus_clk = pll / div;
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return 0;
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}
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ulong get_bus_freq(ulong dummy)
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{
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if (!gd->bus_clk)
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get_clocks();
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return gd->bus_clk;
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}
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ulong get_ddr_freq(ulong dummy)
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{
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if (!gd->mem_clk)
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get_clocks();
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return gd->mem_clk;
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}
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