/*
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* Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <asm/arch/pinmux.h>
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#include <asm/io.h>
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#include <common.h>
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#include <fdtdec.h>
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static int do_pinctr_pin(const void *blob, int child, const char *node_name)
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{
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int len;
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fdt_addr_t base_addr;
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fdt_size_t size;
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const u32 *cell;
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u32 offset, value;
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base_addr = fdtdec_get_addr_size(blob, child, "reg", &size);
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if (base_addr != FDT_ADDR_T_NONE) {
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cell = fdt_getprop(blob, child, "pinctrl-single,pins", &len);
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if (!cell || len <= 0)
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return -EFAULT;
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debug("%p %d\n", cell, len);
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for (; len > 0; len -= (2 * sizeof(u32))) {
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offset = fdt32_to_cpu(*cell++);
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value = fdt32_to_cpu(*cell++);
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debug("<0x%x 0x%x>\n", offset, value);
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writel(value, base_addr + offset);
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}
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return 0;
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}
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return -EFAULT;
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}
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static int do_pinctrl_pins(const void *blob, int node, const char *child_name)
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{
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int child, len;
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const char *node_name;
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child = fdt_first_subnode(blob, node);
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if (child < 0)
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return -EINVAL;
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node_name = fdt_get_name(blob, child, &len);
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while (node_name) {
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if (!strcmp(child_name, node_name))
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return do_pinctr_pin(blob, child, node_name);
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child = fdt_next_subnode(blob, child);
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if (child < 0)
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break;
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node_name = fdt_get_name(blob, child, &len);
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}
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return -EFAULT;
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}
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int config_dedicated_pins(const void *blob)
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{
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int node;
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node = fdtdec_next_compatible(blob, 0,
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COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
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if (node < 0)
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return -EINVAL;
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if (do_pinctrl_pins(blob, node, "dedicated_cfg"))
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return -EFAULT;
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if (do_pinctrl_pins(blob, node, "dedicated"))
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return -EFAULT;
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return 0;
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}
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int config_pins(const void *blob, const char *pin_grp)
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{
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int node;
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node = fdtdec_next_compatible(blob, 0,
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COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
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if (node < 0)
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return -EINVAL;
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if (do_pinctrl_pins(blob, node, pin_grp))
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return -EFAULT;
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return 0;
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}
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