// SPDX-License-Identifier: GPL-2.0
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/*
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* Hantro VPU codec driver
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*
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* Copyright (C) 2018 Rockchip Electronics Co., Ltd.
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* Jeffy Chen <jeffy.chen@rock-chips.com>
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*/
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#include <linux/clk.h>
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#include "hantro.h"
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#include "hantro_jpeg.h"
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#include "hantro_g1_regs.h"
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#include "hantro_h1_regs.h"
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#define RK3288_ACLK_MAX_FREQ (400 * 1000 * 1000)
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/*
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* Supported formats.
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*/
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static const struct hantro_fmt rk3288_vpu_enc_fmts[] = {
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{
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.fourcc = V4L2_PIX_FMT_YUV420M,
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.codec_mode = HANTRO_MODE_NONE,
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.enc_fmt = RK3288_VPU_ENC_FMT_YUV420P,
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},
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{
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.fourcc = V4L2_PIX_FMT_NV12M,
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.codec_mode = HANTRO_MODE_NONE,
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.enc_fmt = RK3288_VPU_ENC_FMT_YUV420SP,
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},
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{
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.fourcc = V4L2_PIX_FMT_YUYV,
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.codec_mode = HANTRO_MODE_NONE,
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.enc_fmt = RK3288_VPU_ENC_FMT_YUYV422,
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},
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{
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.fourcc = V4L2_PIX_FMT_UYVY,
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.codec_mode = HANTRO_MODE_NONE,
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.enc_fmt = RK3288_VPU_ENC_FMT_UYVY422,
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},
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{
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.fourcc = V4L2_PIX_FMT_JPEG,
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.codec_mode = HANTRO_MODE_JPEG_ENC,
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.max_depth = 2,
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.header_size = JPEG_HEADER_SIZE,
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.frmsize = {
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.min_width = 96,
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.max_width = 8192,
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.step_width = MB_DIM,
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.min_height = 32,
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.max_height = 8192,
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.step_height = MB_DIM,
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},
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},
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};
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static const struct hantro_fmt rk3288_vpu_postproc_fmts[] = {
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{
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.fourcc = V4L2_PIX_FMT_YUYV,
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.codec_mode = HANTRO_MODE_NONE,
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},
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};
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static const struct hantro_fmt rk3288_vpu_dec_fmts[] = {
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{
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.fourcc = V4L2_PIX_FMT_NV12,
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.codec_mode = HANTRO_MODE_NONE,
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},
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{
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.fourcc = V4L2_PIX_FMT_H264_SLICE,
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.codec_mode = HANTRO_MODE_H264_DEC,
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.max_depth = 2,
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.frmsize = {
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.min_width = 48,
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.max_width = 4096,
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.step_width = MB_DIM,
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.min_height = 48,
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.max_height = 2304,
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.step_height = MB_DIM,
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},
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},
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{
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.fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
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.codec_mode = HANTRO_MODE_MPEG2_DEC,
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.max_depth = 2,
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.frmsize = {
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.min_width = 48,
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.max_width = 1920,
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.step_width = MB_DIM,
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.min_height = 48,
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.max_height = 1088,
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.step_height = MB_DIM,
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},
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},
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{
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.fourcc = V4L2_PIX_FMT_VP8_FRAME,
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.codec_mode = HANTRO_MODE_VP8_DEC,
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.max_depth = 2,
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.frmsize = {
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.min_width = 48,
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.max_width = 3840,
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.step_width = MB_DIM,
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.min_height = 48,
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.max_height = 2160,
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.step_height = MB_DIM,
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},
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},
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};
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static irqreturn_t rk3288_vepu_irq(int irq, void *dev_id)
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{
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struct hantro_dev *vpu = dev_id;
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enum vb2_buffer_state state;
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u32 status;
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status = vepu_read(vpu, H1_REG_INTERRUPT);
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state = (status & H1_REG_INTERRUPT_FRAME_RDY) ?
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VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
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vepu_write(vpu, 0, H1_REG_INTERRUPT);
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vepu_write(vpu, 0, H1_REG_AXI_CTRL);
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hantro_irq_done(vpu, state);
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return IRQ_HANDLED;
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}
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static irqreturn_t rk3288_vdpu_irq(int irq, void *dev_id)
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{
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struct hantro_dev *vpu = dev_id;
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enum vb2_buffer_state state;
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u32 status;
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status = vdpu_read(vpu, G1_REG_INTERRUPT);
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state = (status & G1_REG_INTERRUPT_DEC_RDY_INT) ?
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VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
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vdpu_write(vpu, 0, G1_REG_INTERRUPT);
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vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG);
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hantro_irq_done(vpu, state);
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return IRQ_HANDLED;
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}
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static int rk3288_vpu_hw_init(struct hantro_dev *vpu)
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{
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/* Bump ACLK to max. possible freq. to improve performance. */
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clk_set_rate(vpu->clocks[0].clk, RK3288_ACLK_MAX_FREQ);
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return 0;
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}
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static void rk3288_vpu_enc_reset(struct hantro_ctx *ctx)
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{
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struct hantro_dev *vpu = ctx->dev;
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vepu_write(vpu, H1_REG_INTERRUPT_DIS_BIT, H1_REG_INTERRUPT);
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vepu_write(vpu, 0, H1_REG_ENC_CTRL);
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vepu_write(vpu, 0, H1_REG_AXI_CTRL);
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}
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static void rk3288_vpu_dec_reset(struct hantro_ctx *ctx)
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{
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struct hantro_dev *vpu = ctx->dev;
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vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT);
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vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG);
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vdpu_write(vpu, 1, G1_REG_SOFT_RESET);
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}
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/*
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* Supported codec ops.
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*/
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static const struct hantro_codec_ops rk3288_vpu_codec_ops[] = {
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[HANTRO_MODE_JPEG_ENC] = {
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.run = hantro_h1_jpeg_enc_run,
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.reset = rk3288_vpu_enc_reset,
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.init = hantro_jpeg_enc_init,
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.done = hantro_jpeg_enc_done,
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.exit = hantro_jpeg_enc_exit,
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},
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[HANTRO_MODE_H264_DEC] = {
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.run = hantro_g1_h264_dec_run,
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.reset = rk3288_vpu_dec_reset,
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.init = hantro_h264_dec_init,
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.exit = hantro_h264_dec_exit,
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},
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[HANTRO_MODE_MPEG2_DEC] = {
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.run = hantro_g1_mpeg2_dec_run,
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.reset = rk3288_vpu_dec_reset,
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.init = hantro_mpeg2_dec_init,
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.exit = hantro_mpeg2_dec_exit,
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},
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[HANTRO_MODE_VP8_DEC] = {
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.run = hantro_g1_vp8_dec_run,
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.reset = rk3288_vpu_dec_reset,
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.init = hantro_vp8_dec_init,
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.exit = hantro_vp8_dec_exit,
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},
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};
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/*
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* VPU variant.
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*/
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static const struct hantro_irq rk3288_irqs[] = {
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{ "vepu", rk3288_vepu_irq },
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{ "vdpu", rk3288_vdpu_irq },
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};
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static const char * const rk3288_clk_names[] = {
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"aclk", "hclk"
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};
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const struct hantro_variant rk3288_vpu_variant = {
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.enc_offset = 0x0,
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.enc_fmts = rk3288_vpu_enc_fmts,
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.num_enc_fmts = ARRAY_SIZE(rk3288_vpu_enc_fmts),
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.dec_offset = 0x400,
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.dec_fmts = rk3288_vpu_dec_fmts,
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.num_dec_fmts = ARRAY_SIZE(rk3288_vpu_dec_fmts),
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.postproc_fmts = rk3288_vpu_postproc_fmts,
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.num_postproc_fmts = ARRAY_SIZE(rk3288_vpu_postproc_fmts),
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.postproc_regs = &hantro_g1_postproc_regs,
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.codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
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HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
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.codec_ops = rk3288_vpu_codec_ops,
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.irqs = rk3288_irqs,
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.num_irqs = ARRAY_SIZE(rk3288_irqs),
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.init = rk3288_vpu_hw_init,
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.clk_names = rk3288_clk_names,
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.num_clocks = ARRAY_SIZE(rk3288_clk_names)
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};
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