/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/* Copyright(c) 2018-2019 Realtek Corporation
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*/
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#ifndef __RTW8822C_H__
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#define __RTW8822C_H__
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#include <asm/byteorder.h>
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struct rtw8822cu_efuse {
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u8 res0[0x30]; /* 0x120 */
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u8 vid[2]; /* 0x150 */
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u8 pid[2];
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u8 res1[3];
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u8 mac_addr[ETH_ALEN]; /* 0x157 */
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u8 res2[0x3d];
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};
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struct rtw8822ce_efuse {
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u8 mac_addr[ETH_ALEN]; /* 0x120 */
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u8 vender_id[2];
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u8 device_id[2];
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u8 sub_vender_id[2];
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u8 sub_device_id[2];
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u8 pmc[2];
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u8 exp_device_cap[2];
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u8 msi_cap;
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u8 ltr_cap; /* 0x133 */
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u8 exp_link_control[2];
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u8 link_cap[4];
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u8 link_control[2];
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u8 serial_number[8];
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u8 res0:2; /* 0x144 */
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u8 ltr_en:1;
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u8 res1:2;
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u8 obff:2;
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u8 res2:3;
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u8 obff_cap:2;
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u8 res3:4;
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u8 class_code[3];
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u8 res4;
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u8 pci_pm_L1_2_supp:1;
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u8 pci_pm_L1_1_supp:1;
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u8 aspm_pm_L1_2_supp:1;
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u8 aspm_pm_L1_1_supp:1;
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u8 L1_pm_substates_supp:1;
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u8 res5:3;
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u8 port_common_mode_restore_time;
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u8 port_t_power_on_scale:2;
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u8 res6:1;
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u8 port_t_power_on_value:5;
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u8 res7;
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};
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struct rtw8822c_efuse {
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__le16 rtl_id;
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u8 res0[0x0e];
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/* power index for four RF paths */
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struct rtw_txpwr_idx txpwr_idx_table[4];
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u8 channel_plan; /* 0xb8 */
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u8 xtal_k;
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u8 res1;
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u8 iqk_lck;
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u8 res2[5]; /* 0xbc */
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u8 rf_board_option;
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u8 rf_feature_option;
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u8 rf_bt_setting;
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u8 eeprom_version;
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u8 eeprom_customer_id;
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u8 tx_bb_swing_setting_2g;
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u8 tx_bb_swing_setting_5g;
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u8 tx_pwr_calibrate_rate;
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u8 rf_antenna_option; /* 0xc9 */
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u8 rfe_option;
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u8 country_code[2];
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u8 res3[3];
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u8 path_a_thermal; /* 0xd0 */
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u8 path_b_thermal;
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u8 res4[2];
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u8 rx_gain_gap_2g_ofdm;
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u8 res5;
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u8 rx_gain_gap_2g_cck;
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u8 res6;
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u8 rx_gain_gap_5gl;
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u8 res7;
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u8 rx_gain_gap_5gm;
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u8 res8;
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u8 rx_gain_gap_5gh;
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u8 res9;
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u8 res10[0x42];
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union {
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struct rtw8822cu_efuse u;
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struct rtw8822ce_efuse e;
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};
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};
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enum rtw8822c_dpk_agc_phase {
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RTW_DPK_GAIN_CHECK,
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RTW_DPK_GAIN_LARGE,
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RTW_DPK_GAIN_LESS,
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RTW_DPK_GL_LARGE,
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RTW_DPK_GL_LESS,
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RTW_DPK_LOSS_CHECK,
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RTW_DPK_AGC_OUT,
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};
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enum rtw8822c_dpk_one_shot_action {
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RTW_DPK_CAL_PWR,
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RTW_DPK_GAIN_LOSS,
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RTW_DPK_DO_DPK,
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RTW_DPK_DPK_ON,
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RTW_DPK_DAGC,
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RTW_DPK_ACTION_MAX
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};
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void rtw8822c_parse_tbl_dpk(struct rtw_dev *rtwdev,
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const struct rtw_table *tbl);
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#define RTW_DECL_TABLE_DPK(name) \
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const struct rtw_table name ## _tbl = { \
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.data = name, \
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.size = ARRAY_SIZE(name), \
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.parse = rtw8822c_parse_tbl_dpk, \
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}
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#define DACK_PATH_8822C 2
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#define DACK_REG_8822C 16
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#define DACK_RF_8822C 1
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#define DACK_SN_8822C 100
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/* phy status page0 */
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#define GET_PHY_STAT_P0_PWDB_A(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
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#define GET_PHY_STAT_P0_PWDB_B(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
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#define GET_PHY_STAT_P0_GAIN_A(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(21, 16))
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#define GET_PHY_STAT_P0_GAIN_B(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(29, 24))
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/* phy status page1 */
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#define GET_PHY_STAT_P1_PWDB_A(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
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#define GET_PHY_STAT_P1_PWDB_B(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
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#define GET_PHY_STAT_P1_L_RXSC(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
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#define GET_PHY_STAT_P1_HT_RXSC(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
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#define GET_PHY_STAT_P1_RXEVM_A(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
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#define GET_PHY_STAT_P1_RXEVM_B(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(15, 8))
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#define GET_PHY_STAT_P1_CFO_TAIL_A(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0))
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#define GET_PHY_STAT_P1_CFO_TAIL_B(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(15, 8))
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#define GET_PHY_STAT_P1_RXSNR_A(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0))
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#define GET_PHY_STAT_P1_RXSNR_B(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(15, 8))
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#define REG_ANAPARLDO_POW_MAC 0x0029
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#define BIT_LDOE25_PON BIT(0)
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#define REG_RRSR 0x0440
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#define BITS_RRSR_RSC (BIT(21) | BIT(22))
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#define REG_TXDFIR0 0x808
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#define REG_DFIRBW 0x810
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#define REG_ANTMAP0 0x820
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#define REG_ANTMAP 0x824
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#define REG_DYMPRITH 0x86c
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#define REG_DYMENTH0 0x870
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#define REG_DYMENTH 0x874
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#define REG_SBD 0x88c
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#define BITS_SUBTUNE GENMASK(15, 12)
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#define REG_DYMTHMIN 0x8a4
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#define REG_TXBWCTL 0x9b0
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#define REG_TXCLK 0x9b4
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#define REG_SCOTRK 0xc30
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#define REG_MRCM 0xc38
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#define REG_AGCSWSH 0xc44
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#define REG_ANTWTPD 0xc54
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#define REG_PT_CHSMO 0xcbc
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#define BIT_PT_OPT BIT(21)
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#define REG_ORITXCODE 0x1800
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#define REG_3WIRE 0x180c
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#define BIT_3WIRE_TX_EN BIT(0)
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#define BIT_3WIRE_RX_EN BIT(1)
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#define BIT_3WIRE_PI_ON BIT(28)
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#define REG_ANAPAR_A 0x1830
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#define BIT_ANAPAR_UPDATE BIT(29)
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#define REG_RXAGCCTL0 0x18ac
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#define BITS_RXAGC_CCK GENMASK(15, 12)
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#define BITS_RXAGC_OFDM GENMASK(8, 4)
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#define REG_DCKA_I_0 0x18bc
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#define REG_DCKA_I_1 0x18c0
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#define REG_DCKA_Q_0 0x18d8
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#define REG_DCKA_Q_1 0x18dc
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#define REG_CCKSB 0x1a00
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#define REG_RXCCKSEL 0x1a04
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#define REG_BGCTRL 0x1a14
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#define BITS_RX_IQ_WEIGHT (BIT(8) | BIT(9))
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#define REG_TXF0 0x1a20
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#define REG_TXF1 0x1a24
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#define REG_TXF2 0x1a28
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#define REG_CCANRX 0x1a2c
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#define BIT_CCK_FA_RST (BIT(14) | BIT(15))
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#define BIT_OFDM_FA_RST (BIT(12) | BIT(13))
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#define REG_CCK_FACNT 0x1a5c
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#define REG_CCKTXONLY 0x1a80
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#define BIT_BB_CCK_CHECK_EN BIT(18)
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#define REG_TXF3 0x1a98
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#define REG_TXF4 0x1a9c
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#define REG_TXF5 0x1aa0
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#define REG_TXF6 0x1aac
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#define REG_TXF7 0x1ab0
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#define REG_CCK_SOURCE 0x1abc
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#define BIT_NBI_EN BIT(30)
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#define REG_IQKSTAT 0x1b10
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#define REG_TXANT 0x1c28
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#define REG_ENCCK 0x1c3c
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#define BIT_CCK_BLK_EN BIT(1)
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#define BIT_CCK_OFDM_BLK_EN (BIT(0) | BIT(1))
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#define REG_CCAMSK 0x1c80
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#define REG_RSTB 0x1c90
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#define BIT_RSTB_3WIRE BIT(8)
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#define REG_RX_BREAK 0x1d2c
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#define BIT_COM_RX_GCK_EN BIT(31)
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#define REG_RXFNCTL 0x1d30
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#define REG_RXIGI 0x1d70
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#define REG_ENFN 0x1e24
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#define REG_TXANTSEG 0x1e28
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#define REG_TXLGMAP 0x1e2c
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#define REG_CCKPATH 0x1e5c
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#define REG_CNT_CTRL 0x1eb4
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#define BIT_ALL_CNT_RST BIT(25)
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#define REG_OFDM_FACNT 0x2d00
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#define REG_OFDM_FACNT1 0x2d04
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#define REG_OFDM_FACNT2 0x2d08
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#define REG_OFDM_FACNT3 0x2d0c
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#define REG_OFDM_FACNT4 0x2d10
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#define REG_OFDM_FACNT5 0x2d20
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#define REG_RPT_CIP 0x2d9c
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#define REG_OFDM_TXCNT 0x2de0
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#define REG_ORITXCODE2 0x4100
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#define REG_3WIRE2 0x410c
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#define REG_ANAPAR_B 0x4130
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#define REG_RXAGCCTL 0x41ac
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#define REG_DCKB_I_0 0x41bc
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#define REG_DCKB_I_1 0x41c0
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#define REG_DCKB_Q_0 0x41d8
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#define REG_DCKB_Q_1 0x41dc
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#define RF_MODE_TRXAGC 0x00
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#define RF_RXAGC_OFFSET 0x19
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#define RF_BW_TRXBB 0x1a
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#define RF_TX_GAIN_OFFSET 0x55
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#define RF_TX_GAIN 0x56
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#define RF_TXA_LB_SW 0x63
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#define RF_RXG_GAIN 0x87
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#define RF_RXA_MIX_GAIN 0x8a
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#define RF_EXT_TIA_BW 0x8f
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#define RF_DEBUG 0xde
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#define REG_NCTL0 0x1b00
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#define REG_DPD_CTL0_S0 0x1b04
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#define REG_DPD_CTL1_S0 0x1b08
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#define REG_IQK_CTL1 0x1b20
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#define REG_DPD_LUT0 0x1b44
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#define REG_DPD_CTL0_S1 0x1b5c
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#define REG_DPD_LUT3 0x1b60
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#define REG_DPD_CTL1_S1 0x1b60
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#define REG_DPD_AGC 0x1b67
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#define REG_DPD_CTL0 0x1bb4
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#define REG_R_CONFIG 0x1bcc
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#define REG_RXSRAM_CTL 0x1bd4
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#define REG_DPD_CTL11 0x1be4
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#define REG_DPD_CTL12 0x1be8
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#define REG_DPD_CTL15 0x1bf4
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#define REG_DPD_CTL16 0x1bf8
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#define REG_STAT_RPT 0x1bfc
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#define BIT_EXT_TIA_BW BIT(1)
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#define BIT_DE_TRXBW BIT(2)
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#define BIT_DE_TX_GAIN BIT(16)
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#define BIT_RXG_GAIN BIT(18)
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#define BIT_DE_PWR_TRIM BIT(19)
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#define BIT_INNER_LB BIT(21)
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#define BIT_BYPASS_DPD BIT(25)
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#define BIT_DPD_EN BIT(31)
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#define BIT_SUBPAGE GENMASK(3, 0)
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#define BIT_TXAGC GENMASK(4, 0)
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#define BIT_GAIN_TXBB GENMASK(4, 0)
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#define BIT_LB_ATT GENMASK(4, 2)
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#define BIT_RXA_MIX_GAIN GENMASK(4, 3)
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#define BIT_IQ_SWITCH GENMASK(5, 0)
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#define BIT_DPD_CLK GENMASK(7, 4)
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#define BIT_RXAGC GENMASK(9, 5)
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#define BIT_BW_RXBB GENMASK(11, 10)
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#define BIT_LB_SW GENMASK(13, 12)
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#define BIT_BW_TXBB GENMASK(14, 12)
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#define BIT_GLOSS_DB GENMASK(14, 12)
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#define BIT_TXA_LB_ATT GENMASK(15, 14)
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#define BIT_TX_OFFSET_VAL GENMASK(18, 14)
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#define BIT_RPT_SEL GENMASK(20, 16)
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#define BIT_GS_PWSF GENMASK(27, 0)
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#define BIT_RPT_DGAIN GENMASK(27, 16)
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#define BIT_TX_CFIR GENMASK(31, 30)
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#define PPG_THERMAL_A 0x1ef
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#define PPG_THERMAL_B 0x1b0
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#define RF_THEMAL_MASK GENMASK(19, 16)
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#define PPG_2GL_TXAB 0x1d4
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#define PPG_2GM_TXAB 0x1ee
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#define PPG_2GH_TXAB 0x1d2
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#define PPG_2G_A_MASK GENMASK(3, 0)
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#define PPG_2G_B_MASK GENMASK(7, 4)
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#define PPG_5GL1_TXA 0x1ec
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#define PPG_5GL2_TXA 0x1e8
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#define PPG_5GM1_TXA 0x1e4
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#define PPG_5GM2_TXA 0x1e0
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#define PPG_5GH1_TXA 0x1dc
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#define PPG_5GL1_TXB 0x1eb
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#define PPG_5GL2_TXB 0x1e7
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#define PPG_5GM1_TXB 0x1e3
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#define PPG_5GM2_TXB 0x1df
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#define PPG_5GH1_TXB 0x1db
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#define PPG_5G_MASK GENMASK(4, 0)
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#define PPG_PABIAS_2GA 0x1d6
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#define PPG_PABIAS_2GB 0x1d5
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#define PPG_PABIAS_5GA 0x1d8
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#define PPG_PABIAS_5GB 0x1d7
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#define PPG_PABIAS_MASK GENMASK(3, 0)
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#define RF_PABIAS_2G_MASK GENMASK(15, 12)
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#define RF_PABIAS_5G_MASK GENMASK(19, 16)
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#endif
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