/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/* Copyright(c) 2018-2019 Realtek Corporation
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*/
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#ifndef __RTW_PHY_H_
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#define __RTW_PHY_H_
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#include "debug.h"
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extern u8 rtw_cck_rates[];
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extern u8 rtw_ofdm_rates[];
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extern u8 rtw_ht_1s_rates[];
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extern u8 rtw_ht_2s_rates[];
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extern u8 rtw_vht_1s_rates[];
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extern u8 rtw_vht_2s_rates[];
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extern u8 *rtw_rate_section[];
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extern u8 rtw_rate_size[];
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void rtw_phy_init(struct rtw_dev *rtwdev);
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void rtw_phy_dynamic_mechanism(struct rtw_dev *rtwdev);
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u8 rtw_phy_rf_power_2_rssi(s8 *rf_power, u8 path_num);
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u32 rtw_phy_read_rf(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
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u32 addr, u32 mask);
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u32 rtw_phy_read_rf_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
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u32 addr, u32 mask);
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bool rtw_phy_write_rf_reg_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
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u32 addr, u32 mask, u32 data);
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bool rtw_phy_write_rf_reg(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
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u32 addr, u32 mask, u32 data);
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bool rtw_phy_write_rf_reg_mix(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
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u32 addr, u32 mask, u32 data);
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void rtw_phy_setup_phy_cond(struct rtw_dev *rtwdev, u32 pkg);
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void rtw_parse_tbl_phy_cond(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
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void rtw_parse_tbl_bb_pg(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
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void rtw_parse_tbl_txpwr_lmt(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
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void rtw_phy_cfg_mac(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
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u32 addr, u32 data);
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void rtw_phy_cfg_agc(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
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u32 addr, u32 data);
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void rtw_phy_cfg_bb(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
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u32 addr, u32 data);
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void rtw_phy_cfg_rf(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
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u32 addr, u32 data);
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void rtw_phy_init_tx_power(struct rtw_dev *rtwdev);
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void rtw_phy_load_tables(struct rtw_dev *rtwdev);
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u8 rtw_phy_get_tx_power_index(struct rtw_dev *rtwdev, u8 rf_path, u8 rate,
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enum rtw_bandwidth bw, u8 channel, u8 regd);
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void rtw_phy_set_tx_power_level(struct rtw_dev *rtwdev, u8 channel);
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void rtw_phy_tx_power_by_rate_config(struct rtw_hal *hal);
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void rtw_phy_tx_power_limit_config(struct rtw_hal *hal);
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void rtw_phy_pwrtrack_avg(struct rtw_dev *rtwdev, u8 thermal, u8 path);
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bool rtw_phy_pwrtrack_thermal_changed(struct rtw_dev *rtwdev, u8 thermal,
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u8 path);
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u8 rtw_phy_pwrtrack_get_delta(struct rtw_dev *rtwdev, u8 path);
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s8 rtw_phy_pwrtrack_get_pwridx(struct rtw_dev *rtwdev,
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struct rtw_swing_table *swing_table,
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u8 tbl_path, u8 therm_path, u8 delta);
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bool rtw_phy_pwrtrack_need_lck(struct rtw_dev *rtwdev);
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bool rtw_phy_pwrtrack_need_iqk(struct rtw_dev *rtwdev);
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void rtw_phy_config_swing_table(struct rtw_dev *rtwdev,
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struct rtw_swing_table *swing_table);
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struct rtw_txpwr_lmt_cfg_pair {
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u8 regd;
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u8 band;
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u8 bw;
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u8 rs;
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u8 ch;
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s8 txpwr_lmt;
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};
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struct rtw_phy_pg_cfg_pair {
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u32 band;
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u32 rf_path;
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u32 tx_num;
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u32 addr;
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u32 bitmask;
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u32 data;
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};
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#define RTW_DECL_TABLE_PHY_COND_CORE(name, cfg, path) \
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const struct rtw_table name ## _tbl = { \
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.data = name, \
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.size = ARRAY_SIZE(name), \
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.parse = rtw_parse_tbl_phy_cond, \
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.do_cfg = cfg, \
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.rf_path = path, \
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}
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#define RTW_DECL_TABLE_PHY_COND(name, cfg) \
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RTW_DECL_TABLE_PHY_COND_CORE(name, cfg, 0)
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#define RTW_DECL_TABLE_RF_RADIO(name, path) \
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RTW_DECL_TABLE_PHY_COND_CORE(name, rtw_phy_cfg_rf, RF_PATH_ ## path)
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#define RTW_DECL_TABLE_BB_PG(name) \
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const struct rtw_table name ## _tbl = { \
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.data = name, \
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.size = ARRAY_SIZE(name), \
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.parse = rtw_parse_tbl_bb_pg, \
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}
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#define RTW_DECL_TABLE_TXPWR_LMT(name) \
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const struct rtw_table name ## _tbl = { \
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.data = name, \
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.size = ARRAY_SIZE(name), \
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.parse = rtw_parse_tbl_txpwr_lmt, \
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}
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static inline const struct rtw_rfe_def *rtw_get_rfe_def(struct rtw_dev *rtwdev)
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{
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struct rtw_chip_info *chip = rtwdev->chip;
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struct rtw_efuse *efuse = &rtwdev->efuse;
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const struct rtw_rfe_def *rfe_def = NULL;
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if (chip->rfe_defs_size == 0)
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return NULL;
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if (efuse->rfe_option < chip->rfe_defs_size)
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rfe_def = &chip->rfe_defs[efuse->rfe_option];
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rtw_dbg(rtwdev, RTW_DBG_PHY, "use rfe_def[%d]\n", efuse->rfe_option);
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return rfe_def;
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}
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static inline int rtw_check_supported_rfe(struct rtw_dev *rtwdev)
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{
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const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev);
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if (!rfe_def || !rfe_def->phy_pg_tbl || !rfe_def->txpwr_lmt_tbl) {
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rtw_err(rtwdev, "rfe %d isn't supported\n",
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rtwdev->efuse.rfe_option);
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return -ENODEV;
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}
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return 0;
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}
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void rtw_phy_dig_write(struct rtw_dev *rtwdev, u8 igi);
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struct rtw_power_params {
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u8 pwr_base;
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s8 pwr_offset;
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s8 pwr_limit;
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s8 pwr_remnant;
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};
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void
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rtw_get_tx_power_params(struct rtw_dev *rtwdev, u8 path,
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u8 rate, u8 bw, u8 ch, u8 regd,
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struct rtw_power_params *pwr_param);
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enum rtw_phy_cck_pd_lv {
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CCK_PD_LV0,
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CCK_PD_LV1,
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CCK_PD_LV2,
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CCK_PD_LV3,
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CCK_PD_LV4,
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CCK_PD_LV_MAX,
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};
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#define MASKBYTE0 0xff
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#define MASKBYTE1 0xff00
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#define MASKBYTE2 0xff0000
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#define MASKBYTE3 0xff000000
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#define MASKHWORD 0xffff0000
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#define MASKLWORD 0x0000ffff
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#define MASKDWORD 0xffffffff
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#define RFREG_MASK 0xfffff
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#define MASK7BITS 0x7f
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#define MASK12BITS 0xfff
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#define MASKH4BITS 0xf0000000
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#define MASK20BITS 0xfffff
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#define MASK24BITS 0xffffff
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#define MASKH3BYTES 0xffffff00
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#define MASKL3BYTES 0x00ffffff
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#define MASKBYTE2HIGHNIBBLE 0x00f00000
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#define MASKBYTE3LOWNIBBLE 0x0f000000
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#define MASKL3BYTES 0x00ffffff
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#define CCK_FA_AVG_RESET 0xffffffff
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#define LSSI_READ_ADDR_MASK 0x7f800000
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#define LSSI_READ_EDGE_MASK 0x80000000
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#define LSSI_READ_DATA_MASK 0xfffff
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#endif
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