/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/* Copyright(c) 2018-2019 Realtek Corporation
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*/
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#ifndef __RTK_PCI_H_
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#define __RTK_PCI_H_
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#define RTK_DEFAULT_TX_DESC_NUM 128
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#define RTK_BEQ_TX_DESC_NUM 256
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#define RTK_MAX_RX_DESC_NUM 512
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/* 11K + rx desc size */
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#define RTK_PCI_RX_BUF_SIZE (11454 + 24)
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#define RTK_PCI_CTRL 0x300
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#define BIT_RST_TRXDMA_INTF BIT(20)
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#define BIT_RX_TAG_EN BIT(15)
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#define REG_DBI_WDATA_V1 0x03E8
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#define REG_DBI_RDATA_V1 0x03EC
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#define REG_DBI_FLAG_V1 0x03F0
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#define BIT_DBI_RFLAG BIT(17)
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#define BIT_DBI_WFLAG BIT(16)
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#define BITS_DBI_WREN GENMASK(15, 12)
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#define BITS_DBI_ADDR_MASK GENMASK(11, 2)
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#define REG_MDIO_V1 0x03F4
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#define REG_PCIE_MIX_CFG 0x03F8
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#define BITS_MDIO_ADDR_MASK GENMASK(4, 0)
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#define BIT_MDIO_WFLAG_V1 BIT(5)
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#define RTW_PCI_MDIO_PG_SZ BIT(5)
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#define RTW_PCI_MDIO_PG_OFFS_G1 0
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#define RTW_PCI_MDIO_PG_OFFS_G2 2
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#define RTW_PCI_WR_RETRY_CNT 20
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#define RTK_PCIE_LINK_CFG 0x0719
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#define BIT_CLKREQ_SW_EN BIT(4)
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#define BIT_L1_SW_EN BIT(3)
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#define RTK_PCIE_CLKDLY_CTRL 0x0725
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#define BIT_PCI_BCNQ_FLAG BIT(4)
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#define RTK_PCI_TXBD_DESA_BCNQ 0x308
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#define RTK_PCI_TXBD_DESA_H2CQ 0x1320
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#define RTK_PCI_TXBD_DESA_MGMTQ 0x310
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#define RTK_PCI_TXBD_DESA_BKQ 0x330
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#define RTK_PCI_TXBD_DESA_BEQ 0x328
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#define RTK_PCI_TXBD_DESA_VIQ 0x320
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#define RTK_PCI_TXBD_DESA_VOQ 0x318
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#define RTK_PCI_TXBD_DESA_HI0Q 0x340
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#define RTK_PCI_RXBD_DESA_MPDUQ 0x338
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#define TRX_BD_IDX_MASK GENMASK(11, 0)
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/* BCNQ is specialized for rsvd page, does not need to specify a number */
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#define RTK_PCI_TXBD_NUM_H2CQ 0x1328
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#define RTK_PCI_TXBD_NUM_MGMTQ 0x380
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#define RTK_PCI_TXBD_NUM_BKQ 0x38A
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#define RTK_PCI_TXBD_NUM_BEQ 0x388
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#define RTK_PCI_TXBD_NUM_VIQ 0x386
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#define RTK_PCI_TXBD_NUM_VOQ 0x384
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#define RTK_PCI_TXBD_NUM_HI0Q 0x38C
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#define RTK_PCI_RXBD_NUM_MPDUQ 0x382
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#define RTK_PCI_TXBD_IDX_H2CQ 0x132C
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#define RTK_PCI_TXBD_IDX_MGMTQ 0x3B0
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#define RTK_PCI_TXBD_IDX_BKQ 0x3AC
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#define RTK_PCI_TXBD_IDX_BEQ 0x3A8
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#define RTK_PCI_TXBD_IDX_VIQ 0x3A4
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#define RTK_PCI_TXBD_IDX_VOQ 0x3A0
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#define RTK_PCI_TXBD_IDX_HI0Q 0x3B8
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#define RTK_PCI_RXBD_IDX_MPDUQ 0x3B4
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#define RTK_PCI_TXBD_RWPTR_CLR 0x39C
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#define RTK_PCI_TXBD_H2CQ_CSR 0x1330
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#define BIT_CLR_H2CQ_HOST_IDX BIT(16)
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#define BIT_CLR_H2CQ_HW_IDX BIT(8)
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#define RTK_PCI_HIMR0 0x0B0
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#define RTK_PCI_HISR0 0x0B4
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#define RTK_PCI_HIMR1 0x0B8
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#define RTK_PCI_HISR1 0x0BC
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#define RTK_PCI_HIMR2 0x10B0
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#define RTK_PCI_HISR2 0x10B4
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#define RTK_PCI_HIMR3 0x10B8
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#define RTK_PCI_HISR3 0x10BC
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/* IMR 0 */
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#define IMR_TIMER2 BIT(31)
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#define IMR_TIMER1 BIT(30)
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#define IMR_PSTIMEOUT BIT(29)
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#define IMR_GTINT4 BIT(28)
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#define IMR_GTINT3 BIT(27)
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#define IMR_TBDER BIT(26)
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#define IMR_TBDOK BIT(25)
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#define IMR_TSF_BIT32_TOGGLE BIT(24)
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#define IMR_BCNDMAINT0 BIT(20)
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#define IMR_BCNDOK0 BIT(16)
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#define IMR_HSISR_IND_ON_INT BIT(15)
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#define IMR_BCNDMAINT_E BIT(14)
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#define IMR_ATIMEND BIT(12)
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#define IMR_HISR1_IND_INT BIT(11)
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#define IMR_C2HCMD BIT(10)
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#define IMR_CPWM2 BIT(9)
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#define IMR_CPWM BIT(8)
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#define IMR_HIGHDOK BIT(7)
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#define IMR_MGNTDOK BIT(6)
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#define IMR_BKDOK BIT(5)
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#define IMR_BEDOK BIT(4)
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#define IMR_VIDOK BIT(3)
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#define IMR_VODOK BIT(2)
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#define IMR_RDU BIT(1)
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#define IMR_ROK BIT(0)
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/* IMR 1 */
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#define IMR_TXFIFO_TH_INT BIT(30)
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#define IMR_BTON_STS_UPDATE BIT(29)
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#define IMR_MCUERR BIT(28)
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#define IMR_BCNDMAINT7 BIT(27)
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#define IMR_BCNDMAINT6 BIT(26)
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#define IMR_BCNDMAINT5 BIT(25)
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#define IMR_BCNDMAINT4 BIT(24)
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#define IMR_BCNDMAINT3 BIT(23)
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#define IMR_BCNDMAINT2 BIT(22)
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#define IMR_BCNDMAINT1 BIT(21)
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#define IMR_BCNDOK7 BIT(20)
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#define IMR_BCNDOK6 BIT(19)
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#define IMR_BCNDOK5 BIT(18)
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#define IMR_BCNDOK4 BIT(17)
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#define IMR_BCNDOK3 BIT(16)
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#define IMR_BCNDOK2 BIT(15)
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#define IMR_BCNDOK1 BIT(14)
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#define IMR_ATIMEND_E BIT(13)
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#define IMR_ATIMEND BIT(12)
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#define IMR_TXERR BIT(11)
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#define IMR_RXERR BIT(10)
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#define IMR_TXFOVW BIT(9)
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#define IMR_RXFOVW BIT(8)
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#define IMR_CPU_MGQ_TXDONE BIT(5)
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#define IMR_PS_TIMER_C BIT(4)
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#define IMR_PS_TIMER_B BIT(3)
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#define IMR_PS_TIMER_A BIT(2)
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#define IMR_CPUMGQ_TX_TIMER BIT(1)
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/* IMR 3 */
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#define IMR_H2CDOK BIT(16)
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/* one element is reserved to know if the ring is closed */
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static inline int avail_desc(u32 wp, u32 rp, u32 len)
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{
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if (rp > wp)
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return rp - wp - 1;
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else
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return len - wp + rp - 1;
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}
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#define RTK_PCI_TXBD_OWN_OFFSET 15
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#define RTK_PCI_TXBD_BCN_WORK 0x383
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struct rtw_pci_tx_buffer_desc {
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__le16 buf_size;
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__le16 psb_len;
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__le32 dma;
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};
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struct rtw_pci_tx_data {
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dma_addr_t dma;
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u8 sn;
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};
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struct rtw_pci_ring {
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u8 *head;
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dma_addr_t dma;
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u8 desc_size;
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u32 len;
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u32 wp;
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u32 rp;
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};
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struct rtw_pci_tx_ring {
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struct rtw_pci_ring r;
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struct sk_buff_head queue;
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bool queue_stopped;
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};
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struct rtw_pci_rx_buffer_desc {
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__le16 buf_size;
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__le16 total_pkt_size;
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__le32 dma;
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};
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struct rtw_pci_rx_ring {
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struct rtw_pci_ring r;
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struct sk_buff *buf[RTK_MAX_RX_DESC_NUM];
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};
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#define RX_TAG_MAX 8192
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struct rtw_pci {
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struct pci_dev *pdev;
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/* Used for PCI interrupt. */
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spinlock_t hwirq_lock;
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/* Used for PCI TX queueing. */
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spinlock_t irq_lock;
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u32 irq_mask[4];
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bool irq_enabled;
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u16 rx_tag;
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DECLARE_BITMAP(tx_queued, RTK_MAX_TX_QUEUE_NUM);
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struct rtw_pci_tx_ring tx_rings[RTK_MAX_TX_QUEUE_NUM];
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struct rtw_pci_rx_ring rx_rings[RTK_MAX_RX_QUEUE_NUM];
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u16 link_ctrl;
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void __iomem *mmap;
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};
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static inline u32 max_num_of_tx_queue(u8 queue)
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{
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u32 max_num;
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switch (queue) {
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case RTW_TX_QUEUE_BE:
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max_num = RTK_BEQ_TX_DESC_NUM;
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break;
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case RTW_TX_QUEUE_BCN:
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max_num = 1;
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break;
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default:
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max_num = RTK_DEFAULT_TX_DESC_NUM;
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break;
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}
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return max_num;
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}
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static inline struct
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rtw_pci_tx_data *rtw_pci_get_tx_data(struct sk_buff *skb)
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{
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struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
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BUILD_BUG_ON(sizeof(struct rtw_pci_tx_data) >
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sizeof(info->status.status_driver_data));
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return (struct rtw_pci_tx_data *)info->status.status_driver_data;
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}
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static inline
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struct rtw_pci_tx_buffer_desc *get_tx_buffer_desc(struct rtw_pci_tx_ring *ring,
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u32 size)
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{
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u8 *buf_desc;
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buf_desc = ring->r.head + ring->r.wp * size;
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return (struct rtw_pci_tx_buffer_desc *)buf_desc;
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}
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#endif
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