// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
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<http://rt2x00.serialmonkey.com>
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*/
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/*
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Module: rt2x00mmio
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Abstract: rt2x00 generic mmio device routines.
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*/
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#include <linux/dma-mapping.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include "rt2x00.h"
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#include "rt2x00mmio.h"
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/*
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* Register access.
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*/
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int rt2x00mmio_regbusy_read(struct rt2x00_dev *rt2x00dev,
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const unsigned int offset,
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const struct rt2x00_field32 field,
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u32 *reg)
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{
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unsigned int i;
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if (!test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags))
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return 0;
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for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
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*reg = rt2x00mmio_register_read(rt2x00dev, offset);
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if (!rt2x00_get_field32(*reg, field))
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return 1;
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udelay(REGISTER_BUSY_DELAY);
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}
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printk_once(KERN_ERR "%s() Indirect register access failed: "
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"offset=0x%.08x, value=0x%.08x\n", __func__, offset, *reg);
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*reg = ~0;
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return 0;
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}
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EXPORT_SYMBOL_GPL(rt2x00mmio_regbusy_read);
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bool rt2x00mmio_rxdone(struct rt2x00_dev *rt2x00dev)
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{
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struct data_queue *queue = rt2x00dev->rx;
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struct queue_entry *entry;
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struct queue_entry_priv_mmio *entry_priv;
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struct skb_frame_desc *skbdesc;
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int max_rx = 16;
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while (--max_rx) {
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entry = rt2x00queue_get_entry(queue, Q_INDEX);
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entry_priv = entry->priv_data;
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if (rt2x00dev->ops->lib->get_entry_state(entry))
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break;
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/*
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* Fill in desc fields of the skb descriptor
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*/
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skbdesc = get_skb_frame_desc(entry->skb);
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skbdesc->desc = entry_priv->desc;
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skbdesc->desc_len = entry->queue->desc_size;
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/*
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* DMA is already done, notify rt2x00lib that
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* it finished successfully.
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*/
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rt2x00lib_dmastart(entry);
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rt2x00lib_dmadone(entry);
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/*
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* Send the frame to rt2x00lib for further processing.
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*/
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rt2x00lib_rxdone(entry, GFP_ATOMIC);
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}
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return !max_rx;
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}
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EXPORT_SYMBOL_GPL(rt2x00mmio_rxdone);
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void rt2x00mmio_flush_queue(struct data_queue *queue, bool drop)
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{
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unsigned int i;
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for (i = 0; !rt2x00queue_empty(queue) && i < 10; i++)
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msleep(50);
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}
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EXPORT_SYMBOL_GPL(rt2x00mmio_flush_queue);
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/*
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* Device initialization handlers.
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*/
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static int rt2x00mmio_alloc_queue_dma(struct rt2x00_dev *rt2x00dev,
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struct data_queue *queue)
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{
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struct queue_entry_priv_mmio *entry_priv;
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void *addr;
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dma_addr_t dma;
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unsigned int i;
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/*
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* Allocate DMA memory for descriptor and buffer.
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*/
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addr = dma_alloc_coherent(rt2x00dev->dev,
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queue->limit * queue->desc_size, &dma,
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GFP_KERNEL);
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if (!addr)
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return -ENOMEM;
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/*
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* Initialize all queue entries to contain valid addresses.
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*/
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for (i = 0; i < queue->limit; i++) {
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entry_priv = queue->entries[i].priv_data;
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entry_priv->desc = addr + i * queue->desc_size;
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entry_priv->desc_dma = dma + i * queue->desc_size;
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}
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return 0;
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}
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static void rt2x00mmio_free_queue_dma(struct rt2x00_dev *rt2x00dev,
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struct data_queue *queue)
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{
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struct queue_entry_priv_mmio *entry_priv =
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queue->entries[0].priv_data;
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if (entry_priv->desc)
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dma_free_coherent(rt2x00dev->dev,
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queue->limit * queue->desc_size,
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entry_priv->desc, entry_priv->desc_dma);
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entry_priv->desc = NULL;
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}
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int rt2x00mmio_initialize(struct rt2x00_dev *rt2x00dev)
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{
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struct data_queue *queue;
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int status;
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/*
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* Allocate DMA
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*/
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queue_for_each(rt2x00dev, queue) {
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status = rt2x00mmio_alloc_queue_dma(rt2x00dev, queue);
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if (status)
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goto exit;
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}
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/*
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* Register interrupt handler.
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*/
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status = request_irq(rt2x00dev->irq,
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rt2x00dev->ops->lib->irq_handler,
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IRQF_SHARED, rt2x00dev->name, rt2x00dev);
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if (status) {
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rt2x00_err(rt2x00dev, "IRQ %d allocation failed (error %d)\n",
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rt2x00dev->irq, status);
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goto exit;
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}
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return 0;
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exit:
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queue_for_each(rt2x00dev, queue)
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rt2x00mmio_free_queue_dma(rt2x00dev, queue);
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return status;
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}
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EXPORT_SYMBOL_GPL(rt2x00mmio_initialize);
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void rt2x00mmio_uninitialize(struct rt2x00_dev *rt2x00dev)
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{
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struct data_queue *queue;
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/*
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* Free irq line.
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*/
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free_irq(rt2x00dev->irq, rt2x00dev);
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/*
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* Free DMA
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*/
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queue_for_each(rt2x00dev, queue)
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rt2x00mmio_free_queue_dma(rt2x00dev, queue);
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}
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EXPORT_SYMBOL_GPL(rt2x00mmio_uninitialize);
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/*
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* rt2x00mmio module information.
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*/
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MODULE_AUTHOR(DRV_PROJECT);
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MODULE_VERSION(DRV_VERSION);
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MODULE_DESCRIPTION("rt2x00 mmio library");
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MODULE_LICENSE("GPL");
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