// SPDX-License-Identifier: GPL-2.0-only
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/*
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* PHY support for Xenon SDHC
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*
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* Copyright (C) 2016 Marvell, All Rights Reserved.
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*
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* Author: Hu Ziji <huziji@marvell.com>
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* Date: 2016-8-24
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*/
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/ktime.h>
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#include <linux/of_address.h>
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#include "sdhci-pltfm.h"
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#include "sdhci-xenon.h"
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/* Register base for eMMC PHY 5.0 Version */
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#define XENON_EMMC_5_0_PHY_REG_BASE 0x0160
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/* Register base for eMMC PHY 5.1 Version */
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#define XENON_EMMC_PHY_REG_BASE 0x0170
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#define XENON_EMMC_PHY_TIMING_ADJUST XENON_EMMC_PHY_REG_BASE
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#define XENON_EMMC_5_0_PHY_TIMING_ADJUST XENON_EMMC_5_0_PHY_REG_BASE
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#define XENON_TIMING_ADJUST_SLOW_MODE BIT(29)
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#define XENON_TIMING_ADJUST_SDIO_MODE BIT(28)
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#define XENON_SAMPL_INV_QSP_PHASE_SELECT BIT(18)
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#define XENON_SAMPL_INV_QSP_PHASE_SELECT_SHIFT 18
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#define XENON_PHY_INITIALIZAION BIT(31)
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#define XENON_WAIT_CYCLE_BEFORE_USING_MASK 0xF
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#define XENON_WAIT_CYCLE_BEFORE_USING_SHIFT 12
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#define XENON_FC_SYNC_EN_DURATION_MASK 0xF
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#define XENON_FC_SYNC_EN_DURATION_SHIFT 8
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#define XENON_FC_SYNC_RST_EN_DURATION_MASK 0xF
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#define XENON_FC_SYNC_RST_EN_DURATION_SHIFT 4
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#define XENON_FC_SYNC_RST_DURATION_MASK 0xF
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#define XENON_FC_SYNC_RST_DURATION_SHIFT 0
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#define XENON_EMMC_PHY_FUNC_CONTROL (XENON_EMMC_PHY_REG_BASE + 0x4)
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#define XENON_EMMC_5_0_PHY_FUNC_CONTROL \
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(XENON_EMMC_5_0_PHY_REG_BASE + 0x4)
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#define XENON_ASYNC_DDRMODE_MASK BIT(23)
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#define XENON_ASYNC_DDRMODE_SHIFT 23
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#define XENON_CMD_DDR_MODE BIT(16)
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#define XENON_DQ_DDR_MODE_SHIFT 8
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#define XENON_DQ_DDR_MODE_MASK 0xFF
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#define XENON_DQ_ASYNC_MODE BIT(4)
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#define XENON_EMMC_PHY_PAD_CONTROL (XENON_EMMC_PHY_REG_BASE + 0x8)
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#define XENON_EMMC_5_0_PHY_PAD_CONTROL \
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(XENON_EMMC_5_0_PHY_REG_BASE + 0x8)
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#define XENON_REC_EN_SHIFT 24
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#define XENON_REC_EN_MASK 0xF
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#define XENON_FC_DQ_RECEN BIT(24)
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#define XENON_FC_CMD_RECEN BIT(25)
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#define XENON_FC_QSP_RECEN BIT(26)
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#define XENON_FC_QSN_RECEN BIT(27)
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#define XENON_OEN_QSN BIT(28)
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#define XENON_AUTO_RECEN_CTRL BIT(30)
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#define XENON_FC_ALL_CMOS_RECEIVER 0xF000
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#define XENON_EMMC5_FC_QSP_PD BIT(18)
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#define XENON_EMMC5_FC_QSP_PU BIT(22)
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#define XENON_EMMC5_FC_CMD_PD BIT(17)
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#define XENON_EMMC5_FC_CMD_PU BIT(21)
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#define XENON_EMMC5_FC_DQ_PD BIT(16)
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#define XENON_EMMC5_FC_DQ_PU BIT(20)
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#define XENON_EMMC_PHY_PAD_CONTROL1 (XENON_EMMC_PHY_REG_BASE + 0xC)
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#define XENON_EMMC5_1_FC_QSP_PD BIT(9)
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#define XENON_EMMC5_1_FC_QSP_PU BIT(25)
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#define XENON_EMMC5_1_FC_CMD_PD BIT(8)
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#define XENON_EMMC5_1_FC_CMD_PU BIT(24)
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#define XENON_EMMC5_1_FC_DQ_PD 0xFF
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#define XENON_EMMC5_1_FC_DQ_PU (0xFF << 16)
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#define XENON_EMMC_PHY_PAD_CONTROL2 (XENON_EMMC_PHY_REG_BASE + 0x10)
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#define XENON_EMMC_5_0_PHY_PAD_CONTROL2 \
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(XENON_EMMC_5_0_PHY_REG_BASE + 0xC)
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#define XENON_ZNR_MASK 0x1F
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#define XENON_ZNR_SHIFT 8
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#define XENON_ZPR_MASK 0x1F
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/* Preferred ZNR and ZPR value vary between different boards.
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* The specific ZNR and ZPR value should be defined here
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* according to board actual timing.
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*/
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#define XENON_ZNR_DEF_VALUE 0xF
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#define XENON_ZPR_DEF_VALUE 0xF
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#define XENON_EMMC_PHY_DLL_CONTROL (XENON_EMMC_PHY_REG_BASE + 0x14)
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#define XENON_EMMC_5_0_PHY_DLL_CONTROL \
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(XENON_EMMC_5_0_PHY_REG_BASE + 0x10)
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#define XENON_DLL_ENABLE BIT(31)
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#define XENON_DLL_UPDATE_STROBE_5_0 BIT(30)
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#define XENON_DLL_REFCLK_SEL BIT(30)
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#define XENON_DLL_UPDATE BIT(23)
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#define XENON_DLL_PHSEL1_SHIFT 24
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#define XENON_DLL_PHSEL0_SHIFT 16
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#define XENON_DLL_PHASE_MASK 0x3F
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#define XENON_DLL_PHASE_90_DEGREE 0x1F
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#define XENON_DLL_FAST_LOCK BIT(5)
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#define XENON_DLL_GAIN2X BIT(3)
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#define XENON_DLL_BYPASS_EN BIT(0)
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#define XENON_EMMC_5_0_PHY_LOGIC_TIMING_ADJUST \
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(XENON_EMMC_5_0_PHY_REG_BASE + 0x14)
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#define XENON_EMMC_5_0_PHY_LOGIC_TIMING_VALUE 0x5A54
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#define XENON_EMMC_PHY_LOGIC_TIMING_ADJUST (XENON_EMMC_PHY_REG_BASE + 0x18)
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#define XENON_LOGIC_TIMING_VALUE 0x00AA8977
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/*
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* List offset of PHY registers and some special register values
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* in eMMC PHY 5.0 or eMMC PHY 5.1
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*/
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struct xenon_emmc_phy_regs {
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/* Offset of Timing Adjust register */
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u16 timing_adj;
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/* Offset of Func Control register */
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u16 func_ctrl;
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/* Offset of Pad Control register */
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u16 pad_ctrl;
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/* Offset of Pad Control register 2 */
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u16 pad_ctrl2;
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/* Offset of DLL Control register */
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u16 dll_ctrl;
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/* Offset of Logic Timing Adjust register */
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u16 logic_timing_adj;
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/* DLL Update Enable bit */
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u32 dll_update;
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/* value in Logic Timing Adjustment register */
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u32 logic_timing_val;
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};
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static const char * const phy_types[] = {
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"emmc 5.0 phy",
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"emmc 5.1 phy"
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};
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enum xenon_phy_type_enum {
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EMMC_5_0_PHY,
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EMMC_5_1_PHY,
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NR_PHY_TYPES
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};
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enum soc_pad_ctrl_type {
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SOC_PAD_SD,
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SOC_PAD_FIXED_1_8V,
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};
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struct soc_pad_ctrl {
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/* Register address of SoC PHY PAD ctrl */
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void __iomem *reg;
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/* SoC PHY PAD ctrl type */
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enum soc_pad_ctrl_type pad_type;
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/* SoC specific operation to set SoC PHY PAD */
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void (*set_soc_pad)(struct sdhci_host *host,
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unsigned char signal_voltage);
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};
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static struct xenon_emmc_phy_regs xenon_emmc_5_0_phy_regs = {
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.timing_adj = XENON_EMMC_5_0_PHY_TIMING_ADJUST,
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.func_ctrl = XENON_EMMC_5_0_PHY_FUNC_CONTROL,
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.pad_ctrl = XENON_EMMC_5_0_PHY_PAD_CONTROL,
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.pad_ctrl2 = XENON_EMMC_5_0_PHY_PAD_CONTROL2,
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.dll_ctrl = XENON_EMMC_5_0_PHY_DLL_CONTROL,
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.logic_timing_adj = XENON_EMMC_5_0_PHY_LOGIC_TIMING_ADJUST,
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.dll_update = XENON_DLL_UPDATE_STROBE_5_0,
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.logic_timing_val = XENON_EMMC_5_0_PHY_LOGIC_TIMING_VALUE,
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};
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static struct xenon_emmc_phy_regs xenon_emmc_5_1_phy_regs = {
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.timing_adj = XENON_EMMC_PHY_TIMING_ADJUST,
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.func_ctrl = XENON_EMMC_PHY_FUNC_CONTROL,
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.pad_ctrl = XENON_EMMC_PHY_PAD_CONTROL,
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.pad_ctrl2 = XENON_EMMC_PHY_PAD_CONTROL2,
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.dll_ctrl = XENON_EMMC_PHY_DLL_CONTROL,
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.logic_timing_adj = XENON_EMMC_PHY_LOGIC_TIMING_ADJUST,
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.dll_update = XENON_DLL_UPDATE,
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.logic_timing_val = XENON_LOGIC_TIMING_VALUE,
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};
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/*
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* eMMC PHY configuration and operations
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*/
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struct xenon_emmc_phy_params {
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bool slow_mode;
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u8 znr;
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u8 zpr;
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/* Nr of consecutive Sampling Points of a Valid Sampling Window */
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u8 nr_tun_times;
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/* Divider for calculating Tuning Step */
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u8 tun_step_divider;
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struct soc_pad_ctrl pad_ctrl;
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};
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static int xenon_alloc_emmc_phy(struct sdhci_host *host)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
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struct xenon_emmc_phy_params *params;
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params = devm_kzalloc(mmc_dev(host->mmc), sizeof(*params), GFP_KERNEL);
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if (!params)
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return -ENOMEM;
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priv->phy_params = params;
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if (priv->phy_type == EMMC_5_0_PHY)
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priv->emmc_phy_regs = &xenon_emmc_5_0_phy_regs;
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else
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priv->emmc_phy_regs = &xenon_emmc_5_1_phy_regs;
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return 0;
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}
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/*
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* eMMC 5.0/5.1 PHY init/re-init.
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* eMMC PHY init should be executed after:
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* 1. SDCLK frequency changes.
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* 2. SDCLK is stopped and re-enabled.
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* 3. config in emmc_phy_regs->timing_adj and emmc_phy_regs->func_ctrl
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* are changed
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*/
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static int xenon_emmc_phy_init(struct sdhci_host *host)
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{
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u32 reg;
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u32 wait, clock;
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
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struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs;
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reg = sdhci_readl(host, phy_regs->timing_adj);
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reg |= XENON_PHY_INITIALIZAION;
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sdhci_writel(host, reg, phy_regs->timing_adj);
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/* Add duration of FC_SYNC_RST */
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wait = ((reg >> XENON_FC_SYNC_RST_DURATION_SHIFT) &
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XENON_FC_SYNC_RST_DURATION_MASK);
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/* Add interval between FC_SYNC_EN and FC_SYNC_RST */
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wait += ((reg >> XENON_FC_SYNC_RST_EN_DURATION_SHIFT) &
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XENON_FC_SYNC_RST_EN_DURATION_MASK);
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/* Add duration of asserting FC_SYNC_EN */
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wait += ((reg >> XENON_FC_SYNC_EN_DURATION_SHIFT) &
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XENON_FC_SYNC_EN_DURATION_MASK);
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/* Add duration of waiting for PHY */
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wait += ((reg >> XENON_WAIT_CYCLE_BEFORE_USING_SHIFT) &
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XENON_WAIT_CYCLE_BEFORE_USING_MASK);
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/* 4 additional bus clock and 4 AXI bus clock are required */
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wait += 8;
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wait <<= 20;
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clock = host->clock;
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if (!clock)
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/* Use the possibly slowest bus frequency value */
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clock = XENON_LOWEST_SDCLK_FREQ;
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/* get the wait time */
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wait /= clock;
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wait++;
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/* wait for host eMMC PHY init completes */
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udelay(wait);
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reg = sdhci_readl(host, phy_regs->timing_adj);
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reg &= XENON_PHY_INITIALIZAION;
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if (reg) {
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dev_err(mmc_dev(host->mmc), "eMMC PHY init cannot complete after %d us\n",
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wait);
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return -ETIMEDOUT;
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}
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return 0;
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}
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#define ARMADA_3700_SOC_PAD_1_8V 0x1
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#define ARMADA_3700_SOC_PAD_3_3V 0x0
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static void armada_3700_soc_pad_voltage_set(struct sdhci_host *host,
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unsigned char signal_voltage)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
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struct xenon_emmc_phy_params *params = priv->phy_params;
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if (params->pad_ctrl.pad_type == SOC_PAD_FIXED_1_8V) {
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writel(ARMADA_3700_SOC_PAD_1_8V, params->pad_ctrl.reg);
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} else if (params->pad_ctrl.pad_type == SOC_PAD_SD) {
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if (signal_voltage == MMC_SIGNAL_VOLTAGE_180)
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writel(ARMADA_3700_SOC_PAD_1_8V, params->pad_ctrl.reg);
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else if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
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writel(ARMADA_3700_SOC_PAD_3_3V, params->pad_ctrl.reg);
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}
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}
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/*
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* Set SoC PHY voltage PAD control register,
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* according to the operation voltage on PAD.
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* The detailed operation depends on SoC implementation.
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*/
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static void xenon_emmc_phy_set_soc_pad(struct sdhci_host *host,
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unsigned char signal_voltage)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
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struct xenon_emmc_phy_params *params = priv->phy_params;
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if (!params->pad_ctrl.reg)
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return;
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if (params->pad_ctrl.set_soc_pad)
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params->pad_ctrl.set_soc_pad(host, signal_voltage);
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}
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/*
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* Enable eMMC PHY HW DLL
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* DLL should be enabled and stable before HS200/SDR104 tuning,
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* and before HS400 data strobe setting.
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*/
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static int xenon_emmc_phy_enable_dll(struct sdhci_host *host)
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{
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u32 reg;
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
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struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs;
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ktime_t timeout;
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if (WARN_ON(host->clock <= MMC_HIGH_52_MAX_DTR))
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return -EINVAL;
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reg = sdhci_readl(host, phy_regs->dll_ctrl);
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if (reg & XENON_DLL_ENABLE)
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return 0;
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/* Enable DLL */
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reg = sdhci_readl(host, phy_regs->dll_ctrl);
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reg |= (XENON_DLL_ENABLE | XENON_DLL_FAST_LOCK);
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/*
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* Set Phase as 90 degree, which is most common value.
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* Might set another value if necessary.
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* The granularity is 1 degree.
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*/
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reg &= ~((XENON_DLL_PHASE_MASK << XENON_DLL_PHSEL0_SHIFT) |
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(XENON_DLL_PHASE_MASK << XENON_DLL_PHSEL1_SHIFT));
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reg |= ((XENON_DLL_PHASE_90_DEGREE << XENON_DLL_PHSEL0_SHIFT) |
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(XENON_DLL_PHASE_90_DEGREE << XENON_DLL_PHSEL1_SHIFT));
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reg &= ~XENON_DLL_BYPASS_EN;
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reg |= phy_regs->dll_update;
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if (priv->phy_type == EMMC_5_1_PHY)
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reg &= ~XENON_DLL_REFCLK_SEL;
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sdhci_writel(host, reg, phy_regs->dll_ctrl);
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/* Wait max 32 ms */
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timeout = ktime_add_ms(ktime_get(), 32);
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while (1) {
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bool timedout = ktime_after(ktime_get(), timeout);
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if (sdhci_readw(host, XENON_SLOT_EXT_PRESENT_STATE) &
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XENON_DLL_LOCK_STATE)
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break;
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if (timedout) {
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dev_err(mmc_dev(host->mmc), "Wait for DLL Lock time-out\n");
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return -ETIMEDOUT;
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}
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udelay(100);
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}
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return 0;
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}
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/*
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* Config to eMMC PHY to prepare for tuning.
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* Enable HW DLL and set the TUNING_STEP
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*/
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static int xenon_emmc_phy_config_tuning(struct sdhci_host *host)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
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struct xenon_emmc_phy_params *params = priv->phy_params;
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u32 reg, tuning_step;
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int ret;
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if (host->clock <= MMC_HIGH_52_MAX_DTR)
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return -EINVAL;
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ret = xenon_emmc_phy_enable_dll(host);
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if (ret)
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return ret;
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/* Achieve TUNING_STEP with HW DLL help */
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reg = sdhci_readl(host, XENON_SLOT_DLL_CUR_DLY_VAL);
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tuning_step = reg / params->tun_step_divider;
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if (unlikely(tuning_step > XENON_TUNING_STEP_MASK)) {
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dev_warn(mmc_dev(host->mmc),
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"HS200 TUNING_STEP %d is larger than MAX value\n",
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tuning_step);
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tuning_step = XENON_TUNING_STEP_MASK;
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}
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/* Set TUNING_STEP for later tuning */
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reg = sdhci_readl(host, XENON_SLOT_OP_STATUS_CTRL);
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reg &= ~(XENON_TUN_CONSECUTIVE_TIMES_MASK <<
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XENON_TUN_CONSECUTIVE_TIMES_SHIFT);
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reg |= (params->nr_tun_times << XENON_TUN_CONSECUTIVE_TIMES_SHIFT);
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reg &= ~(XENON_TUNING_STEP_MASK << XENON_TUNING_STEP_SHIFT);
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reg |= (tuning_step << XENON_TUNING_STEP_SHIFT);
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sdhci_writel(host, reg, XENON_SLOT_OP_STATUS_CTRL);
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return 0;
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}
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static void xenon_emmc_phy_disable_strobe(struct sdhci_host *host)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
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u32 reg;
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/* Disable both SDHC Data Strobe and Enhanced Strobe */
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reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL);
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reg &= ~(XENON_ENABLE_DATA_STROBE | XENON_ENABLE_RESP_STROBE);
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sdhci_writel(host, reg, XENON_SLOT_EMMC_CTRL);
|
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/* Clear Strobe line Pull down or Pull up */
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if (priv->phy_type == EMMC_5_0_PHY) {
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reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL);
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reg &= ~(XENON_EMMC5_FC_QSP_PD | XENON_EMMC5_FC_QSP_PU);
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sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL);
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} else {
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reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1);
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reg &= ~(XENON_EMMC5_1_FC_QSP_PD | XENON_EMMC5_1_FC_QSP_PU);
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sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1);
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}
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}
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/* Set HS400 Data Strobe and Enhanced Strobe */
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static void xenon_emmc_phy_strobe_delay_adj(struct sdhci_host *host)
|
{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
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u32 reg;
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if (WARN_ON(host->timing != MMC_TIMING_MMC_HS400))
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return;
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if (host->clock <= MMC_HIGH_52_MAX_DTR)
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return;
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dev_dbg(mmc_dev(host->mmc), "starts HS400 strobe delay adjustment\n");
|
|
xenon_emmc_phy_enable_dll(host);
|
|
/* Enable SDHC Data Strobe */
|
reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL);
|
reg |= XENON_ENABLE_DATA_STROBE;
|
/*
|
* Enable SDHC Enhanced Strobe if supported
|
* Xenon Enhanced Strobe should be enabled only when
|
* 1. card is in HS400 mode and
|
* 2. SDCLK is higher than 52MHz
|
* 3. DLL is enabled
|
*/
|
if (host->mmc->ios.enhanced_strobe)
|
reg |= XENON_ENABLE_RESP_STROBE;
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sdhci_writel(host, reg, XENON_SLOT_EMMC_CTRL);
|
|
/* Set Data Strobe Pull down */
|
if (priv->phy_type == EMMC_5_0_PHY) {
|
reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL);
|
reg |= XENON_EMMC5_FC_QSP_PD;
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reg &= ~XENON_EMMC5_FC_QSP_PU;
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sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL);
|
} else {
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reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1);
|
reg |= XENON_EMMC5_1_FC_QSP_PD;
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reg &= ~XENON_EMMC5_1_FC_QSP_PU;
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sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1);
|
}
|
}
|
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/*
|
* If eMMC PHY Slow Mode is required in lower speed mode (SDCLK < 55MHz)
|
* in SDR mode, enable Slow Mode to bypass eMMC PHY.
|
* SDIO slower SDR mode also requires Slow Mode.
|
*
|
* If Slow Mode is enabled, return true.
|
* Otherwise, return false.
|
*/
|
static bool xenon_emmc_phy_slow_mode(struct sdhci_host *host,
|
unsigned char timing)
|
{
|
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
|
struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
|
struct xenon_emmc_phy_params *params = priv->phy_params;
|
struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs;
|
u32 reg;
|
int ret;
|
|
if (host->clock > MMC_HIGH_52_MAX_DTR)
|
return false;
|
|
reg = sdhci_readl(host, phy_regs->timing_adj);
|
/* When in slower SDR mode, enable Slow Mode for SDIO
|
* or when Slow Mode flag is set
|
*/
|
switch (timing) {
|
case MMC_TIMING_LEGACY:
|
/*
|
* If Slow Mode is required, enable Slow Mode by default
|
* in early init phase to avoid any potential issue.
|
*/
|
if (params->slow_mode) {
|
reg |= XENON_TIMING_ADJUST_SLOW_MODE;
|
ret = true;
|
} else {
|
reg &= ~XENON_TIMING_ADJUST_SLOW_MODE;
|
ret = false;
|
}
|
break;
|
case MMC_TIMING_UHS_SDR25:
|
case MMC_TIMING_UHS_SDR12:
|
case MMC_TIMING_SD_HS:
|
case MMC_TIMING_MMC_HS:
|
if ((priv->init_card_type == MMC_TYPE_SDIO) ||
|
params->slow_mode) {
|
reg |= XENON_TIMING_ADJUST_SLOW_MODE;
|
ret = true;
|
break;
|
}
|
fallthrough;
|
default:
|
reg &= ~XENON_TIMING_ADJUST_SLOW_MODE;
|
ret = false;
|
}
|
|
sdhci_writel(host, reg, phy_regs->timing_adj);
|
return ret;
|
}
|
|
/*
|
* Set-up eMMC 5.0/5.1 PHY.
|
* Specific configuration depends on the current speed mode in use.
|
*/
|
static void xenon_emmc_phy_set(struct sdhci_host *host,
|
unsigned char timing)
|
{
|
u32 reg;
|
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
|
struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
|
struct xenon_emmc_phy_params *params = priv->phy_params;
|
struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs;
|
|
dev_dbg(mmc_dev(host->mmc), "eMMC PHY setting starts\n");
|
|
/* Setup pad, set bit[28] and bits[26:24] */
|
reg = sdhci_readl(host, phy_regs->pad_ctrl);
|
reg |= (XENON_FC_DQ_RECEN | XENON_FC_CMD_RECEN |
|
XENON_FC_QSP_RECEN | XENON_OEN_QSN);
|
/* All FC_XX_RECEIVCE should be set as CMOS Type */
|
reg |= XENON_FC_ALL_CMOS_RECEIVER;
|
sdhci_writel(host, reg, phy_regs->pad_ctrl);
|
|
/* Set CMD and DQ Pull Up */
|
if (priv->phy_type == EMMC_5_0_PHY) {
|
reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL);
|
reg |= (XENON_EMMC5_FC_CMD_PU | XENON_EMMC5_FC_DQ_PU);
|
reg &= ~(XENON_EMMC5_FC_CMD_PD | XENON_EMMC5_FC_DQ_PD);
|
sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL);
|
} else {
|
reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1);
|
reg |= (XENON_EMMC5_1_FC_CMD_PU | XENON_EMMC5_1_FC_DQ_PU);
|
reg &= ~(XENON_EMMC5_1_FC_CMD_PD | XENON_EMMC5_1_FC_DQ_PD);
|
sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1);
|
}
|
|
if (timing == MMC_TIMING_LEGACY) {
|
xenon_emmc_phy_slow_mode(host, timing);
|
goto phy_init;
|
}
|
|
/*
|
* If SDIO card, set SDIO Mode
|
* Otherwise, clear SDIO Mode
|
*/
|
reg = sdhci_readl(host, phy_regs->timing_adj);
|
if (priv->init_card_type == MMC_TYPE_SDIO)
|
reg |= XENON_TIMING_ADJUST_SDIO_MODE;
|
else
|
reg &= ~XENON_TIMING_ADJUST_SDIO_MODE;
|
sdhci_writel(host, reg, phy_regs->timing_adj);
|
|
if (xenon_emmc_phy_slow_mode(host, timing))
|
goto phy_init;
|
|
/*
|
* Set preferred ZNR and ZPR value
|
* The ZNR and ZPR value vary between different boards.
|
* Define them both in sdhci-xenon-emmc-phy.h.
|
*/
|
reg = sdhci_readl(host, phy_regs->pad_ctrl2);
|
reg &= ~((XENON_ZNR_MASK << XENON_ZNR_SHIFT) | XENON_ZPR_MASK);
|
reg |= ((params->znr << XENON_ZNR_SHIFT) | params->zpr);
|
sdhci_writel(host, reg, phy_regs->pad_ctrl2);
|
|
/*
|
* When setting EMMC_PHY_FUNC_CONTROL register,
|
* SD clock should be disabled
|
*/
|
reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
|
reg &= ~SDHCI_CLOCK_CARD_EN;
|
sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
|
|
reg = sdhci_readl(host, phy_regs->func_ctrl);
|
switch (timing) {
|
case MMC_TIMING_MMC_HS400:
|
reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |
|
XENON_CMD_DDR_MODE;
|
reg &= ~XENON_DQ_ASYNC_MODE;
|
break;
|
case MMC_TIMING_UHS_DDR50:
|
case MMC_TIMING_MMC_DDR52:
|
reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |
|
XENON_CMD_DDR_MODE | XENON_DQ_ASYNC_MODE;
|
break;
|
default:
|
reg &= ~((XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |
|
XENON_CMD_DDR_MODE);
|
reg |= XENON_DQ_ASYNC_MODE;
|
}
|
sdhci_writel(host, reg, phy_regs->func_ctrl);
|
|
/* Enable bus clock */
|
reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
|
reg |= SDHCI_CLOCK_CARD_EN;
|
sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
|
|
if (timing == MMC_TIMING_MMC_HS400)
|
/* Hardware team recommend a value for HS400 */
|
sdhci_writel(host, phy_regs->logic_timing_val,
|
phy_regs->logic_timing_adj);
|
else
|
xenon_emmc_phy_disable_strobe(host);
|
|
phy_init:
|
xenon_emmc_phy_init(host);
|
|
dev_dbg(mmc_dev(host->mmc), "eMMC PHY setting completes\n");
|
}
|
|
static int get_dt_pad_ctrl_data(struct sdhci_host *host,
|
struct device_node *np,
|
struct xenon_emmc_phy_params *params)
|
{
|
int ret = 0;
|
const char *name;
|
struct resource iomem;
|
|
if (of_device_is_compatible(np, "marvell,armada-3700-sdhci"))
|
params->pad_ctrl.set_soc_pad = armada_3700_soc_pad_voltage_set;
|
else
|
return 0;
|
|
if (of_address_to_resource(np, 1, &iomem)) {
|
dev_err(mmc_dev(host->mmc), "Unable to find SoC PAD ctrl register address for %pOFn\n",
|
np);
|
return -EINVAL;
|
}
|
|
params->pad_ctrl.reg = devm_ioremap_resource(mmc_dev(host->mmc),
|
&iomem);
|
if (IS_ERR(params->pad_ctrl.reg))
|
return PTR_ERR(params->pad_ctrl.reg);
|
|
ret = of_property_read_string(np, "marvell,pad-type", &name);
|
if (ret) {
|
dev_err(mmc_dev(host->mmc), "Unable to determine SoC PHY PAD ctrl type\n");
|
return ret;
|
}
|
if (!strcmp(name, "sd")) {
|
params->pad_ctrl.pad_type = SOC_PAD_SD;
|
} else if (!strcmp(name, "fixed-1-8v")) {
|
params->pad_ctrl.pad_type = SOC_PAD_FIXED_1_8V;
|
} else {
|
dev_err(mmc_dev(host->mmc), "Unsupported SoC PHY PAD ctrl type %s\n",
|
name);
|
return -EINVAL;
|
}
|
|
return ret;
|
}
|
|
static int xenon_emmc_phy_parse_param_dt(struct sdhci_host *host,
|
struct device_node *np,
|
struct xenon_emmc_phy_params *params)
|
{
|
u32 value;
|
|
params->slow_mode = false;
|
if (of_property_read_bool(np, "marvell,xenon-phy-slow-mode"))
|
params->slow_mode = true;
|
|
params->znr = XENON_ZNR_DEF_VALUE;
|
if (!of_property_read_u32(np, "marvell,xenon-phy-znr", &value))
|
params->znr = value & XENON_ZNR_MASK;
|
|
params->zpr = XENON_ZPR_DEF_VALUE;
|
if (!of_property_read_u32(np, "marvell,xenon-phy-zpr", &value))
|
params->zpr = value & XENON_ZPR_MASK;
|
|
params->nr_tun_times = XENON_TUN_CONSECUTIVE_TIMES;
|
if (!of_property_read_u32(np, "marvell,xenon-phy-nr-success-tun",
|
&value))
|
params->nr_tun_times = value & XENON_TUN_CONSECUTIVE_TIMES_MASK;
|
|
params->tun_step_divider = XENON_TUNING_STEP_DIVIDER;
|
if (!of_property_read_u32(np, "marvell,xenon-phy-tun-step-divider",
|
&value))
|
params->tun_step_divider = value & 0xFF;
|
|
return get_dt_pad_ctrl_data(host, np, params);
|
}
|
|
/* Set SoC PHY Voltage PAD */
|
void xenon_soc_pad_ctrl(struct sdhci_host *host,
|
unsigned char signal_voltage)
|
{
|
xenon_emmc_phy_set_soc_pad(host, signal_voltage);
|
}
|
|
/*
|
* Setting PHY when card is working in High Speed Mode.
|
* HS400 set Data Strobe and Enhanced Strobe if it is supported.
|
* HS200/SDR104 set tuning config to prepare for tuning.
|
*/
|
static int xenon_hs_delay_adj(struct sdhci_host *host)
|
{
|
int ret = 0;
|
|
if (WARN_ON(host->clock <= XENON_DEFAULT_SDCLK_FREQ))
|
return -EINVAL;
|
|
switch (host->timing) {
|
case MMC_TIMING_MMC_HS400:
|
xenon_emmc_phy_strobe_delay_adj(host);
|
return 0;
|
case MMC_TIMING_MMC_HS200:
|
case MMC_TIMING_UHS_SDR104:
|
return xenon_emmc_phy_config_tuning(host);
|
case MMC_TIMING_MMC_DDR52:
|
case MMC_TIMING_UHS_DDR50:
|
/*
|
* DDR Mode requires driver to scan Sampling Fixed Delay Line,
|
* to find out a perfect operation sampling point.
|
* It is hard to implement such a scan in host driver
|
* since initiating commands by host driver is not safe.
|
* Thus so far just keep PHY Sampling Fixed Delay in
|
* default value of DDR mode.
|
*
|
* If any timing issue occurs in DDR mode on Marvell products,
|
* please contact maintainer for internal support in Marvell.
|
*/
|
dev_warn_once(mmc_dev(host->mmc), "Timing issue might occur in DDR mode\n");
|
return 0;
|
}
|
|
return ret;
|
}
|
|
/*
|
* Adjust PHY setting.
|
* PHY setting should be adjusted when SDCLK frequency, Bus Width
|
* or Speed Mode is changed.
|
* Additional config are required when card is working in High Speed mode,
|
* after leaving Legacy Mode.
|
*/
|
int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios)
|
{
|
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
|
struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
|
int ret = 0;
|
|
if (!host->clock) {
|
priv->clock = 0;
|
return 0;
|
}
|
|
/*
|
* The timing, frequency or bus width is changed,
|
* better to set eMMC PHY based on current setting
|
* and adjust Xenon SDHC delay.
|
*/
|
if ((host->clock == priv->clock) &&
|
(ios->bus_width == priv->bus_width) &&
|
(ios->timing == priv->timing))
|
return 0;
|
|
xenon_emmc_phy_set(host, ios->timing);
|
|
/* Update the record */
|
priv->bus_width = ios->bus_width;
|
|
priv->timing = ios->timing;
|
priv->clock = host->clock;
|
|
/* Legacy mode is a special case */
|
if (ios->timing == MMC_TIMING_LEGACY)
|
return 0;
|
|
if (host->clock > XENON_DEFAULT_SDCLK_FREQ)
|
ret = xenon_hs_delay_adj(host);
|
return ret;
|
}
|
|
static int xenon_add_phy(struct device_node *np, struct sdhci_host *host,
|
const char *phy_name)
|
{
|
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
|
struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
|
int ret;
|
|
priv->phy_type = match_string(phy_types, NR_PHY_TYPES, phy_name);
|
if (priv->phy_type < 0) {
|
dev_err(mmc_dev(host->mmc),
|
"Unable to determine PHY name %s. Use default eMMC 5.1 PHY\n",
|
phy_name);
|
priv->phy_type = EMMC_5_1_PHY;
|
}
|
|
ret = xenon_alloc_emmc_phy(host);
|
if (ret)
|
return ret;
|
|
return xenon_emmc_phy_parse_param_dt(host, np, priv->phy_params);
|
}
|
|
int xenon_phy_parse_dt(struct device_node *np, struct sdhci_host *host)
|
{
|
const char *phy_type = NULL;
|
|
if (!of_property_read_string(np, "marvell,xenon-phy-type", &phy_type))
|
return xenon_add_phy(np, host, phy_type);
|
|
return xenon_add_phy(np, host, "emmc 5.1 phy");
|
}
|
