// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2017 SiFive
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* Copyright (C) 2018 Christoph Hellwig
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*/
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#define pr_fmt(fmt) "plic: " fmt
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#include <linux/cpu.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <asm/smp.h>
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/*
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* This driver implements a version of the RISC-V PLIC with the actual layout
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* specified in chapter 8 of the SiFive U5 Coreplex Series Manual:
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*
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* https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf
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*
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* The largest number supported by devices marked as 'sifive,plic-1.0.0', is
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* 1024, of which device 0 is defined as non-existent by the RISC-V Privileged
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* Spec.
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*/
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#define MAX_DEVICES 1024
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#define MAX_CONTEXTS 15872
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/*
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* Each interrupt source has a priority register associated with it.
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* We always hardwire it to one in Linux.
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*/
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#define PRIORITY_BASE 0
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#define PRIORITY_PER_ID 4
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/*
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* Each hart context has a vector of interrupt enable bits associated with it.
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* There's one bit for each interrupt source.
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*/
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#define ENABLE_BASE 0x2000
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#define ENABLE_PER_HART 0x80
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/*
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* Each hart context has a set of control registers associated with it. Right
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* now there's only two: a source priority threshold over which the hart will
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* take an interrupt, and a register to claim interrupts.
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*/
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#define CONTEXT_BASE 0x200000
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#define CONTEXT_PER_HART 0x1000
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#define CONTEXT_THRESHOLD 0x00
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#define CONTEXT_CLAIM 0x04
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#define PLIC_DISABLE_THRESHOLD 0x7
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#define PLIC_ENABLE_THRESHOLD 0
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struct plic_priv {
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struct cpumask lmask;
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struct irq_domain *irqdomain;
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void __iomem *regs;
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};
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struct plic_handler {
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bool present;
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void __iomem *hart_base;
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/*
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* Protect mask operations on the registers given that we can't
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* assume atomic memory operations work on them.
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*/
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raw_spinlock_t enable_lock;
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void __iomem *enable_base;
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struct plic_priv *priv;
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};
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static int plic_parent_irq;
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static bool plic_cpuhp_setup_done;
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static DEFINE_PER_CPU(struct plic_handler, plic_handlers);
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static inline void plic_toggle(struct plic_handler *handler,
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int hwirq, int enable)
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{
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u32 __iomem *reg = handler->enable_base + (hwirq / 32) * sizeof(u32);
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u32 hwirq_mask = 1 << (hwirq % 32);
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raw_spin_lock(&handler->enable_lock);
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if (enable)
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writel(readl(reg) | hwirq_mask, reg);
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else
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writel(readl(reg) & ~hwirq_mask, reg);
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raw_spin_unlock(&handler->enable_lock);
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}
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static inline void plic_irq_toggle(const struct cpumask *mask,
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struct irq_data *d, int enable)
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{
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int cpu;
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struct plic_priv *priv = irq_data_get_irq_chip_data(d);
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writel(enable, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID);
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for_each_cpu(cpu, mask) {
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struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu);
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if (handler->present &&
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cpumask_test_cpu(cpu, &handler->priv->lmask))
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plic_toggle(handler, d->hwirq, enable);
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}
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}
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static void plic_irq_unmask(struct irq_data *d)
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{
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struct cpumask amask;
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unsigned int cpu;
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struct plic_priv *priv = irq_data_get_irq_chip_data(d);
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cpumask_and(&amask, &priv->lmask, cpu_online_mask);
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cpu = cpumask_any_and(irq_data_get_affinity_mask(d),
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&amask);
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if (WARN_ON_ONCE(cpu >= nr_cpu_ids))
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return;
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plic_irq_toggle(cpumask_of(cpu), d, 1);
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}
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static void plic_irq_mask(struct irq_data *d)
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{
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struct plic_priv *priv = irq_data_get_irq_chip_data(d);
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plic_irq_toggle(&priv->lmask, d, 0);
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}
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#ifdef CONFIG_SMP
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static int plic_set_affinity(struct irq_data *d,
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const struct cpumask *mask_val, bool force)
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{
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unsigned int cpu;
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struct cpumask amask;
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struct plic_priv *priv = irq_data_get_irq_chip_data(d);
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cpumask_and(&amask, &priv->lmask, mask_val);
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if (force)
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cpu = cpumask_first(&amask);
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else
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cpu = cpumask_any_and(&amask, cpu_online_mask);
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if (cpu >= nr_cpu_ids)
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return -EINVAL;
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plic_irq_toggle(&priv->lmask, d, 0);
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plic_irq_toggle(cpumask_of(cpu), d, !irqd_irq_masked(d));
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irq_data_update_effective_affinity(d, cpumask_of(cpu));
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return IRQ_SET_MASK_OK_DONE;
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}
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#endif
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static void plic_irq_eoi(struct irq_data *d)
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{
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struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
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if (irqd_irq_masked(d)) {
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plic_irq_unmask(d);
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writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM);
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plic_irq_mask(d);
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} else {
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writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM);
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}
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}
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static struct irq_chip plic_chip = {
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.name = "SiFive PLIC",
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.irq_mask = plic_irq_mask,
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.irq_unmask = plic_irq_unmask,
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.irq_eoi = plic_irq_eoi,
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#ifdef CONFIG_SMP
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.irq_set_affinity = plic_set_affinity,
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#endif
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};
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static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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struct plic_priv *priv = d->host_data;
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irq_domain_set_info(d, irq, hwirq, &plic_chip, d->host_data,
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handle_fasteoi_irq, NULL, NULL);
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irq_set_noprobe(irq);
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irq_set_affinity(irq, &priv->lmask);
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return 0;
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}
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static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *arg)
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{
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int i, ret;
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irq_hw_number_t hwirq;
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unsigned int type;
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struct irq_fwspec *fwspec = arg;
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ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type);
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if (ret)
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return ret;
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for (i = 0; i < nr_irqs; i++) {
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ret = plic_irqdomain_map(domain, virq + i, hwirq + i);
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if (ret)
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return ret;
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}
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return 0;
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}
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static const struct irq_domain_ops plic_irqdomain_ops = {
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.translate = irq_domain_translate_onecell,
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.alloc = plic_irq_domain_alloc,
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.free = irq_domain_free_irqs_top,
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};
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/*
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* Handling an interrupt is a two-step process: first you claim the interrupt
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* by reading the claim register, then you complete the interrupt by writing
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* that source ID back to the same claim register. This automatically enables
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* and disables the interrupt, so there's nothing else to do.
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*/
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static void plic_handle_irq(struct irq_desc *desc)
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{
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struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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void __iomem *claim = handler->hart_base + CONTEXT_CLAIM;
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irq_hw_number_t hwirq;
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WARN_ON_ONCE(!handler->present);
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chained_irq_enter(chip, desc);
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while ((hwirq = readl(claim))) {
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int irq = irq_find_mapping(handler->priv->irqdomain, hwirq);
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if (unlikely(irq <= 0))
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pr_warn_ratelimited("can't find mapping for hwirq %lu\n",
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hwirq);
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else
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generic_handle_irq(irq);
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}
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chained_irq_exit(chip, desc);
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}
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static void plic_set_threshold(struct plic_handler *handler, u32 threshold)
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{
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/* priority must be > threshold to trigger an interrupt */
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writel(threshold, handler->hart_base + CONTEXT_THRESHOLD);
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}
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static int plic_dying_cpu(unsigned int cpu)
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{
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if (plic_parent_irq)
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disable_percpu_irq(plic_parent_irq);
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return 0;
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}
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static int plic_starting_cpu(unsigned int cpu)
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{
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struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
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if (plic_parent_irq)
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enable_percpu_irq(plic_parent_irq,
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irq_get_trigger_type(plic_parent_irq));
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else
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pr_warn("cpu%d: parent irq not available\n", cpu);
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plic_set_threshold(handler, PLIC_ENABLE_THRESHOLD);
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return 0;
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}
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static int __init plic_init(struct device_node *node,
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struct device_node *parent)
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{
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int error = 0, nr_contexts, nr_handlers = 0, i;
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u32 nr_irqs;
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struct plic_priv *priv;
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struct plic_handler *handler;
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priv = kzalloc(sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->regs = of_iomap(node, 0);
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if (WARN_ON(!priv->regs)) {
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error = -EIO;
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goto out_free_priv;
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}
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error = -EINVAL;
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of_property_read_u32(node, "riscv,ndev", &nr_irqs);
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if (WARN_ON(!nr_irqs))
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goto out_iounmap;
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nr_contexts = of_irq_count(node);
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if (WARN_ON(!nr_contexts))
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goto out_iounmap;
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error = -ENOMEM;
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priv->irqdomain = irq_domain_add_linear(node, nr_irqs + 1,
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&plic_irqdomain_ops, priv);
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if (WARN_ON(!priv->irqdomain))
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goto out_iounmap;
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for (i = 0; i < nr_contexts; i++) {
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struct of_phandle_args parent;
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irq_hw_number_t hwirq;
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int cpu, hartid;
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if (of_irq_parse_one(node, i, &parent)) {
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pr_err("failed to parse parent for context %d.\n", i);
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continue;
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}
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/*
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* Skip contexts other than external interrupts for our
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* privilege level.
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*/
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if (parent.args[0] != RV_IRQ_EXT)
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continue;
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hartid = riscv_of_parent_hartid(parent.np);
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if (hartid < 0) {
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pr_warn("failed to parse hart ID for context %d.\n", i);
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continue;
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}
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cpu = riscv_hartid_to_cpuid(hartid);
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if (cpu < 0) {
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pr_warn("Invalid cpuid for context %d\n", i);
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continue;
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}
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/* Find parent domain and register chained handler */
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if (!plic_parent_irq && irq_find_host(parent.np)) {
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plic_parent_irq = irq_of_parse_and_map(node, i);
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if (plic_parent_irq)
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irq_set_chained_handler(plic_parent_irq,
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plic_handle_irq);
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}
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/*
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* When running in M-mode we need to ignore the S-mode handler.
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* Here we assume it always comes later, but that might be a
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* little fragile.
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*/
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handler = per_cpu_ptr(&plic_handlers, cpu);
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if (handler->present) {
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pr_warn("handler already present for context %d.\n", i);
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plic_set_threshold(handler, PLIC_DISABLE_THRESHOLD);
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goto done;
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}
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cpumask_set_cpu(cpu, &priv->lmask);
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handler->present = true;
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handler->hart_base =
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priv->regs + CONTEXT_BASE + i * CONTEXT_PER_HART;
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raw_spin_lock_init(&handler->enable_lock);
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handler->enable_base =
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priv->regs + ENABLE_BASE + i * ENABLE_PER_HART;
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handler->priv = priv;
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done:
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for (hwirq = 1; hwirq <= nr_irqs; hwirq++)
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plic_toggle(handler, hwirq, 0);
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nr_handlers++;
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}
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/*
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* We can have multiple PLIC instances so setup cpuhp state only
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* when context handler for current/boot CPU is present.
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*/
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handler = this_cpu_ptr(&plic_handlers);
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if (handler->present && !plic_cpuhp_setup_done) {
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cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING,
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"irqchip/sifive/plic:starting",
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plic_starting_cpu, plic_dying_cpu);
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plic_cpuhp_setup_done = true;
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}
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pr_info("%pOFP: mapped %d interrupts with %d handlers for"
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" %d contexts.\n", node, nr_irqs, nr_handlers, nr_contexts);
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return 0;
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out_iounmap:
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iounmap(priv->regs);
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out_free_priv:
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kfree(priv);
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return error;
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}
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IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init);
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IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */
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IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_init); /* for firmware driver */
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