/*
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*
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* (C) COPYRIGHT 2010-2014, 2016, 2017 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms
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* of such GNU licence.
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*
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* A copy of the licence is included with the program, and can also be obtained
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* from Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
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* Boston, MA 02110-1301, USA.
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*
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*/
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#include "mali_kbase_mmu_mode.h"
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#include "mali_kbase.h"
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#include "mali_midg_regmap.h"
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#define ENTRY_TYPE_MASK 3ULL
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/* For valid ATEs bit 1 = (level == 3) ? 1 : 0.
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* The MMU is only ever configured by the driver so that ATEs
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* are at level 3, so bit 1 should always be set
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*/
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#define ENTRY_IS_ATE 3ULL
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#define ENTRY_IS_INVAL 2ULL
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#define ENTRY_IS_PTE 3ULL
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#define ENTRY_ATTR_BITS (7ULL << 2) /* bits 4:2 */
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#define ENTRY_ACCESS_RW (1ULL << 6) /* bits 6:7 */
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#define ENTRY_ACCESS_RO (3ULL << 6)
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#define ENTRY_SHARE_BITS (3ULL << 8) /* bits 9:8 */
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#define ENTRY_ACCESS_BIT (1ULL << 10)
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#define ENTRY_NX_BIT (1ULL << 54)
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/* Helper Function to perform assignment of page table entries, to
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* ensure the use of strd, which is required on LPAE systems.
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*/
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static inline void page_table_entry_set(u64 *pte, u64 phy)
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{
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#ifdef CONFIG_64BIT
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*pte = phy;
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#elif defined(CONFIG_ARM)
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/*
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* In order to prevent the compiler keeping cached copies of
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* memory, we have to explicitly say that we have updated memory.
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*
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* Note: We could manually move the data ourselves into R0 and
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* R1 by specifying register variables that are explicitly
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* given registers assignments, the down side of this is that
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* we have to assume cpu endianness. To avoid this we can use
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* the ldrd to read the data from memory into R0 and R1 which
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* will respect the cpu endianness, we then use strd to make
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* the 64 bit assignment to the page table entry.
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*/
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asm volatile("ldrd r0, r1, [%[ptemp]]\n\t"
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"strd r0, r1, [%[pte]]\n\t"
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: "=m" (*pte)
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: [ptemp] "r" (&phy), [pte] "r" (pte), "m" (phy)
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: "r0", "r1");
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#else
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#error "64-bit atomic write must be implemented for your architecture"
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#endif
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}
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static void mmu_get_as_setup(struct kbase_context *kctx,
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struct kbase_mmu_setup * const setup)
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{
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/* Set up the required caching policies at the correct indices
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* in the memattr register.
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*/
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setup->memattr =
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(AS_MEMATTR_IMPL_DEF_CACHE_POLICY <<
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(AS_MEMATTR_INDEX_IMPL_DEF_CACHE_POLICY * 8)) |
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(AS_MEMATTR_FORCE_TO_CACHE_ALL <<
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(AS_MEMATTR_INDEX_FORCE_TO_CACHE_ALL * 8)) |
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(AS_MEMATTR_WRITE_ALLOC <<
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(AS_MEMATTR_INDEX_WRITE_ALLOC * 8)) |
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(AS_MEMATTR_AARCH64_OUTER_IMPL_DEF <<
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(AS_MEMATTR_INDEX_OUTER_IMPL_DEF * 8)) |
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(AS_MEMATTR_AARCH64_OUTER_WA <<
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(AS_MEMATTR_INDEX_OUTER_WA * 8));
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setup->transtab = (u64)kctx->pgd & AS_TRANSTAB_BASE_MASK;
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setup->transcfg = AS_TRANSCFG_ADRMODE_AARCH64_4K;
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}
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static void mmu_update(struct kbase_context *kctx)
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{
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struct kbase_device * const kbdev = kctx->kbdev;
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struct kbase_as * const as = &kbdev->as[kctx->as_nr];
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struct kbase_mmu_setup * const current_setup = &as->current_setup;
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mmu_get_as_setup(kctx, current_setup);
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/* Apply the address space setting */
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kbase_mmu_hw_configure(kbdev, as, kctx);
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}
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static void mmu_disable_as(struct kbase_device *kbdev, int as_nr)
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{
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struct kbase_as * const as = &kbdev->as[as_nr];
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struct kbase_mmu_setup * const current_setup = &as->current_setup;
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current_setup->transtab = 0ULL;
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current_setup->transcfg = AS_TRANSCFG_ADRMODE_UNMAPPED;
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/* Apply the address space setting */
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kbase_mmu_hw_configure(kbdev, as, NULL);
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}
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static phys_addr_t pte_to_phy_addr(u64 entry)
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{
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if (!(entry & 1))
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return 0;
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return entry & ~0xFFF;
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}
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static int ate_is_valid(u64 ate)
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{
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return ((ate & ENTRY_TYPE_MASK) == ENTRY_IS_ATE);
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}
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static int pte_is_valid(u64 pte)
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{
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return ((pte & ENTRY_TYPE_MASK) == ENTRY_IS_PTE);
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}
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/*
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* Map KBASE_REG flags to MMU flags
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*/
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static u64 get_mmu_flags(unsigned long flags)
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{
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u64 mmu_flags;
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/* store mem_attr index as 4:2 (macro called ensures 3 bits already) */
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mmu_flags = KBASE_REG_MEMATTR_VALUE(flags) << 2;
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/* Set access flags - note that AArch64 stage 1 does not support
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* write-only access, so we use read/write instead
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*/
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if (flags & KBASE_REG_GPU_WR)
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mmu_flags |= ENTRY_ACCESS_RW;
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else if (flags & KBASE_REG_GPU_RD)
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mmu_flags |= ENTRY_ACCESS_RO;
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/* nx if requested */
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mmu_flags |= (flags & KBASE_REG_GPU_NX) ? ENTRY_NX_BIT : 0;
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if (flags & KBASE_REG_SHARE_BOTH) {
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/* inner and outer shareable */
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mmu_flags |= SHARE_BOTH_BITS;
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} else if (flags & KBASE_REG_SHARE_IN) {
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/* inner shareable coherency */
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mmu_flags |= SHARE_INNER_BITS;
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}
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return mmu_flags;
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}
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static void entry_set_ate(u64 *entry, phys_addr_t phy, unsigned long flags)
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{
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page_table_entry_set(entry, (phy & ~0xFFF) |
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get_mmu_flags(flags) |
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ENTRY_ACCESS_BIT | ENTRY_IS_ATE);
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}
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static void entry_set_pte(u64 *entry, phys_addr_t phy)
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{
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page_table_entry_set(entry, (phy & ~0xFFF) |
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ENTRY_ACCESS_BIT | ENTRY_IS_PTE);
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}
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static void entry_invalidate(u64 *entry)
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{
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page_table_entry_set(entry, ENTRY_IS_INVAL);
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}
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static struct kbase_mmu_mode const aarch64_mode = {
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.update = mmu_update,
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.get_as_setup = mmu_get_as_setup,
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.disable_as = mmu_disable_as,
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.pte_to_phy_addr = pte_to_phy_addr,
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.ate_is_valid = ate_is_valid,
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.pte_is_valid = pte_is_valid,
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.entry_set_ate = entry_set_ate,
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.entry_set_pte = entry_set_pte,
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.entry_invalidate = entry_invalidate
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};
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struct kbase_mmu_mode const *kbase_mmu_mode_get_aarch64(void)
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{
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return &aarch64_mode;
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}
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