// SPDX-License-Identifier: GPL-2.0
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/* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/workqueue.h>
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#include <linux/aer.h>
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#include <linux/fs.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/device.h>
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#include <linux/idr.h>
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#include <uapi/linux/idxd.h>
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#include <linux/dmaengine.h>
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#include "../dmaengine.h"
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#include "registers.h"
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#include "idxd.h"
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MODULE_VERSION(IDXD_DRIVER_VERSION);
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Intel Corporation");
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#define DRV_NAME "idxd"
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static struct idr idxd_idrs[IDXD_TYPE_MAX];
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static struct mutex idxd_idr_lock;
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static struct pci_device_id idxd_pci_tbl[] = {
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/* DSA ver 1.0 platforms */
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_DSA_SPR0) },
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{ 0, }
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};
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MODULE_DEVICE_TABLE(pci, idxd_pci_tbl);
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static char *idxd_name[] = {
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"dsa",
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};
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const char *idxd_get_dev_name(struct idxd_device *idxd)
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{
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return idxd_name[idxd->type];
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}
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static int idxd_setup_interrupts(struct idxd_device *idxd)
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{
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struct pci_dev *pdev = idxd->pdev;
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struct device *dev = &pdev->dev;
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struct msix_entry *msix;
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struct idxd_irq_entry *irq_entry;
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int i, msixcnt;
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int rc = 0;
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msixcnt = pci_msix_vec_count(pdev);
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if (msixcnt < 0) {
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dev_err(dev, "Not MSI-X interrupt capable.\n");
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goto err_no_irq;
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}
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idxd->msix_entries = devm_kzalloc(dev, sizeof(struct msix_entry) *
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msixcnt, GFP_KERNEL);
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if (!idxd->msix_entries) {
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rc = -ENOMEM;
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goto err_no_irq;
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}
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for (i = 0; i < msixcnt; i++)
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idxd->msix_entries[i].entry = i;
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rc = pci_enable_msix_exact(pdev, idxd->msix_entries, msixcnt);
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if (rc) {
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dev_err(dev, "Failed enabling %d MSIX entries.\n", msixcnt);
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goto err_no_irq;
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}
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dev_dbg(dev, "Enabled %d msix vectors\n", msixcnt);
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/*
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* We implement 1 completion list per MSI-X entry except for
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* entry 0, which is for errors and others.
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*/
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idxd->irq_entries = devm_kcalloc(dev, msixcnt,
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sizeof(struct idxd_irq_entry),
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GFP_KERNEL);
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if (!idxd->irq_entries) {
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rc = -ENOMEM;
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goto err_no_irq;
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}
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for (i = 0; i < msixcnt; i++) {
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idxd->irq_entries[i].id = i;
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idxd->irq_entries[i].idxd = idxd;
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}
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msix = &idxd->msix_entries[0];
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irq_entry = &idxd->irq_entries[0];
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rc = devm_request_threaded_irq(dev, msix->vector, idxd_irq_handler,
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idxd_misc_thread, 0, "idxd-misc",
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irq_entry);
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if (rc < 0) {
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dev_err(dev, "Failed to allocate misc interrupt.\n");
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goto err_no_irq;
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}
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dev_dbg(dev, "Allocated idxd-misc handler on msix vector %d\n",
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msix->vector);
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/* first MSI-X entry is not for wq interrupts */
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idxd->num_wq_irqs = msixcnt - 1;
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for (i = 1; i < msixcnt; i++) {
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msix = &idxd->msix_entries[i];
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irq_entry = &idxd->irq_entries[i];
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init_llist_head(&idxd->irq_entries[i].pending_llist);
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INIT_LIST_HEAD(&idxd->irq_entries[i].work_list);
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rc = devm_request_threaded_irq(dev, msix->vector,
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idxd_irq_handler,
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idxd_wq_thread, 0,
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"idxd-portal", irq_entry);
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if (rc < 0) {
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dev_err(dev, "Failed to allocate irq %d.\n",
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msix->vector);
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goto err_no_irq;
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}
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dev_dbg(dev, "Allocated idxd-msix %d for vector %d\n",
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i, msix->vector);
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}
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idxd_unmask_error_interrupts(idxd);
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return 0;
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err_no_irq:
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/* Disable error interrupt generation */
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idxd_mask_error_interrupts(idxd);
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pci_disable_msix(pdev);
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dev_err(dev, "No usable interrupts\n");
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return rc;
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}
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static int idxd_setup_internals(struct idxd_device *idxd)
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{
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struct device *dev = &idxd->pdev->dev;
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int i;
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init_waitqueue_head(&idxd->cmd_waitq);
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idxd->groups = devm_kcalloc(dev, idxd->max_groups,
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sizeof(struct idxd_group), GFP_KERNEL);
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if (!idxd->groups)
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return -ENOMEM;
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for (i = 0; i < idxd->max_groups; i++) {
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idxd->groups[i].idxd = idxd;
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idxd->groups[i].id = i;
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idxd->groups[i].tc_a = -1;
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idxd->groups[i].tc_b = -1;
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}
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idxd->wqs = devm_kcalloc(dev, idxd->max_wqs, sizeof(struct idxd_wq),
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GFP_KERNEL);
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if (!idxd->wqs)
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return -ENOMEM;
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idxd->engines = devm_kcalloc(dev, idxd->max_engines,
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sizeof(struct idxd_engine), GFP_KERNEL);
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if (!idxd->engines)
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return -ENOMEM;
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for (i = 0; i < idxd->max_wqs; i++) {
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struct idxd_wq *wq = &idxd->wqs[i];
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wq->id = i;
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wq->idxd = idxd;
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mutex_init(&wq->wq_lock);
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init_waitqueue_head(&wq->err_queue);
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wq->max_xfer_bytes = idxd->max_xfer_bytes;
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wq->max_batch_size = idxd->max_batch_size;
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wq->wqcfg = devm_kzalloc(dev, idxd->wqcfg_size, GFP_KERNEL);
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if (!wq->wqcfg)
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return -ENOMEM;
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}
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for (i = 0; i < idxd->max_engines; i++) {
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idxd->engines[i].idxd = idxd;
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idxd->engines[i].id = i;
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}
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idxd->wq = create_workqueue(dev_name(dev));
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if (!idxd->wq)
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return -ENOMEM;
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return 0;
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}
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static void idxd_read_table_offsets(struct idxd_device *idxd)
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{
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union offsets_reg offsets;
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struct device *dev = &idxd->pdev->dev;
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offsets.bits[0] = ioread64(idxd->reg_base + IDXD_TABLE_OFFSET);
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offsets.bits[1] = ioread64(idxd->reg_base + IDXD_TABLE_OFFSET
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+ sizeof(u64));
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idxd->grpcfg_offset = offsets.grpcfg * 0x100;
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dev_dbg(dev, "IDXD Group Config Offset: %#x\n", idxd->grpcfg_offset);
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idxd->wqcfg_offset = offsets.wqcfg * 0x100;
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dev_dbg(dev, "IDXD Work Queue Config Offset: %#x\n",
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idxd->wqcfg_offset);
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idxd->msix_perm_offset = offsets.msix_perm * 0x100;
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dev_dbg(dev, "IDXD MSIX Permission Offset: %#x\n",
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idxd->msix_perm_offset);
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idxd->perfmon_offset = offsets.perfmon * 0x100;
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dev_dbg(dev, "IDXD Perfmon Offset: %#x\n", idxd->perfmon_offset);
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}
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static void idxd_read_caps(struct idxd_device *idxd)
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{
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struct device *dev = &idxd->pdev->dev;
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int i;
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/* reading generic capabilities */
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idxd->hw.gen_cap.bits = ioread64(idxd->reg_base + IDXD_GENCAP_OFFSET);
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dev_dbg(dev, "gen_cap: %#llx\n", idxd->hw.gen_cap.bits);
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idxd->max_xfer_bytes = 1ULL << idxd->hw.gen_cap.max_xfer_shift;
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dev_dbg(dev, "max xfer size: %llu bytes\n", idxd->max_xfer_bytes);
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idxd->max_batch_size = 1U << idxd->hw.gen_cap.max_batch_shift;
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dev_dbg(dev, "max batch size: %u\n", idxd->max_batch_size);
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if (idxd->hw.gen_cap.config_en)
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set_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags);
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/* reading group capabilities */
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idxd->hw.group_cap.bits =
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ioread64(idxd->reg_base + IDXD_GRPCAP_OFFSET);
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dev_dbg(dev, "group_cap: %#llx\n", idxd->hw.group_cap.bits);
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idxd->max_groups = idxd->hw.group_cap.num_groups;
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dev_dbg(dev, "max groups: %u\n", idxd->max_groups);
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idxd->max_tokens = idxd->hw.group_cap.total_tokens;
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dev_dbg(dev, "max tokens: %u\n", idxd->max_tokens);
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idxd->nr_tokens = idxd->max_tokens;
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/* read engine capabilities */
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idxd->hw.engine_cap.bits =
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ioread64(idxd->reg_base + IDXD_ENGCAP_OFFSET);
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dev_dbg(dev, "engine_cap: %#llx\n", idxd->hw.engine_cap.bits);
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idxd->max_engines = idxd->hw.engine_cap.num_engines;
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dev_dbg(dev, "max engines: %u\n", idxd->max_engines);
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/* read workqueue capabilities */
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idxd->hw.wq_cap.bits = ioread64(idxd->reg_base + IDXD_WQCAP_OFFSET);
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dev_dbg(dev, "wq_cap: %#llx\n", idxd->hw.wq_cap.bits);
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idxd->max_wq_size = idxd->hw.wq_cap.total_wq_size;
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dev_dbg(dev, "total workqueue size: %u\n", idxd->max_wq_size);
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idxd->max_wqs = idxd->hw.wq_cap.num_wqs;
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dev_dbg(dev, "max workqueues: %u\n", idxd->max_wqs);
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idxd->wqcfg_size = 1 << (idxd->hw.wq_cap.wqcfg_size + IDXD_WQCFG_MIN);
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dev_dbg(dev, "wqcfg size: %u\n", idxd->wqcfg_size);
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/* reading operation capabilities */
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for (i = 0; i < 4; i++) {
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idxd->hw.opcap.bits[i] = ioread64(idxd->reg_base +
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IDXD_OPCAP_OFFSET + i * sizeof(u64));
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dev_dbg(dev, "opcap[%d]: %#llx\n", i, idxd->hw.opcap.bits[i]);
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}
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}
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static struct idxd_device *idxd_alloc(struct pci_dev *pdev,
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void __iomem * const *iomap)
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{
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struct device *dev = &pdev->dev;
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struct idxd_device *idxd;
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idxd = devm_kzalloc(dev, sizeof(struct idxd_device), GFP_KERNEL);
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if (!idxd)
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return NULL;
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idxd->pdev = pdev;
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idxd->reg_base = iomap[IDXD_MMIO_BAR];
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spin_lock_init(&idxd->dev_lock);
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return idxd;
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}
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static int idxd_probe(struct idxd_device *idxd)
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{
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struct pci_dev *pdev = idxd->pdev;
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struct device *dev = &pdev->dev;
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int rc;
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dev_dbg(dev, "%s entered and resetting device\n", __func__);
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rc = idxd_device_init_reset(idxd);
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if (rc < 0)
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return rc;
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dev_dbg(dev, "IDXD reset complete\n");
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idxd_read_caps(idxd);
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idxd_read_table_offsets(idxd);
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rc = idxd_setup_internals(idxd);
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if (rc)
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goto err_setup;
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rc = idxd_setup_interrupts(idxd);
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if (rc)
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goto err_setup;
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dev_dbg(dev, "IDXD interrupt setup complete.\n");
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mutex_lock(&idxd_idr_lock);
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idxd->id = idr_alloc(&idxd_idrs[idxd->type], idxd, 0, 0, GFP_KERNEL);
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mutex_unlock(&idxd_idr_lock);
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if (idxd->id < 0) {
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rc = -ENOMEM;
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goto err_idr_fail;
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}
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idxd->major = idxd_cdev_get_major(idxd);
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dev_dbg(dev, "IDXD device %d probed successfully\n", idxd->id);
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return 0;
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err_idr_fail:
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idxd_mask_error_interrupts(idxd);
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idxd_mask_msix_vectors(idxd);
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err_setup:
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return rc;
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}
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static int idxd_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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{
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void __iomem * const *iomap;
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struct device *dev = &pdev->dev;
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struct idxd_device *idxd;
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int rc;
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unsigned int mask;
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rc = pcim_enable_device(pdev);
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if (rc)
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return rc;
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dev_dbg(dev, "Mapping BARs\n");
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mask = (1 << IDXD_MMIO_BAR);
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rc = pcim_iomap_regions(pdev, mask, DRV_NAME);
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if (rc)
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return rc;
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iomap = pcim_iomap_table(pdev);
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if (!iomap)
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return -ENOMEM;
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dev_dbg(dev, "Set DMA masks\n");
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rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
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if (rc)
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rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
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if (rc)
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return rc;
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rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
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if (rc)
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rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
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if (rc)
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return rc;
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dev_dbg(dev, "Alloc IDXD context\n");
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idxd = idxd_alloc(pdev, iomap);
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if (!idxd)
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return -ENOMEM;
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idxd_set_type(idxd);
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dev_dbg(dev, "Set PCI master\n");
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pci_set_master(pdev);
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pci_set_drvdata(pdev, idxd);
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idxd->hw.version = ioread32(idxd->reg_base + IDXD_VER_OFFSET);
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rc = idxd_probe(idxd);
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if (rc) {
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dev_err(dev, "Intel(R) IDXD DMA Engine init failed\n");
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return -ENODEV;
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}
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rc = idxd_setup_sysfs(idxd);
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if (rc) {
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dev_err(dev, "IDXD sysfs setup failed\n");
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return -ENODEV;
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}
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idxd->state = IDXD_DEV_CONF_READY;
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dev_info(&pdev->dev, "Intel(R) Accelerator Device (v%x)\n",
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idxd->hw.version);
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return 0;
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}
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static void idxd_flush_pending_llist(struct idxd_irq_entry *ie)
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{
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struct idxd_desc *desc, *itr;
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struct llist_node *head;
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head = llist_del_all(&ie->pending_llist);
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if (!head)
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return;
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llist_for_each_entry_safe(desc, itr, head, llnode) {
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idxd_dma_complete_txd(desc, IDXD_COMPLETE_ABORT);
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idxd_free_desc(desc->wq, desc);
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}
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}
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static void idxd_flush_work_list(struct idxd_irq_entry *ie)
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{
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struct idxd_desc *desc, *iter;
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list_for_each_entry_safe(desc, iter, &ie->work_list, list) {
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list_del(&desc->list);
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idxd_dma_complete_txd(desc, IDXD_COMPLETE_ABORT);
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idxd_free_desc(desc->wq, desc);
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}
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}
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static void idxd_shutdown(struct pci_dev *pdev)
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{
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struct idxd_device *idxd = pci_get_drvdata(pdev);
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int rc, i;
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struct idxd_irq_entry *irq_entry;
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int msixcnt = pci_msix_vec_count(pdev);
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rc = idxd_device_disable(idxd);
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if (rc)
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dev_err(&pdev->dev, "Disabling device failed\n");
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dev_dbg(&pdev->dev, "%s called\n", __func__);
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idxd_mask_msix_vectors(idxd);
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idxd_mask_error_interrupts(idxd);
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for (i = 0; i < msixcnt; i++) {
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irq_entry = &idxd->irq_entries[i];
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synchronize_irq(idxd->msix_entries[i].vector);
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if (i == 0)
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continue;
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idxd_flush_pending_llist(irq_entry);
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idxd_flush_work_list(irq_entry);
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}
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destroy_workqueue(idxd->wq);
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}
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static void idxd_remove(struct pci_dev *pdev)
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{
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struct idxd_device *idxd = pci_get_drvdata(pdev);
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dev_dbg(&pdev->dev, "%s called\n", __func__);
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idxd_cleanup_sysfs(idxd);
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idxd_shutdown(pdev);
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mutex_lock(&idxd_idr_lock);
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idr_remove(&idxd_idrs[idxd->type], idxd->id);
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mutex_unlock(&idxd_idr_lock);
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}
|
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static struct pci_driver idxd_pci_driver = {
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.name = DRV_NAME,
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.id_table = idxd_pci_tbl,
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.probe = idxd_pci_probe,
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.remove = idxd_remove,
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.shutdown = idxd_shutdown,
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};
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static int __init idxd_init_module(void)
|
{
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int err, i;
|
|
/*
|
* If the CPU does not support write512, there's no point in
|
* enumerating the device. We can not utilize it.
|
*/
|
if (!boot_cpu_has(X86_FEATURE_MOVDIR64B)) {
|
pr_warn("idxd driver failed to load without MOVDIR64B.\n");
|
return -ENODEV;
|
}
|
|
pr_info("%s: Intel(R) Accelerator Devices Driver %s\n",
|
DRV_NAME, IDXD_DRIVER_VERSION);
|
|
mutex_init(&idxd_idr_lock);
|
for (i = 0; i < IDXD_TYPE_MAX; i++)
|
idr_init(&idxd_idrs[i]);
|
|
err = idxd_register_bus_type();
|
if (err < 0)
|
return err;
|
|
err = idxd_register_driver();
|
if (err < 0)
|
goto err_idxd_driver_register;
|
|
err = idxd_cdev_register();
|
if (err)
|
goto err_cdev_register;
|
|
err = pci_register_driver(&idxd_pci_driver);
|
if (err)
|
goto err_pci_register;
|
|
return 0;
|
|
err_pci_register:
|
idxd_cdev_remove();
|
err_cdev_register:
|
idxd_unregister_driver();
|
err_idxd_driver_register:
|
idxd_unregister_bus_type();
|
return err;
|
}
|
module_init(idxd_init_module);
|
|
static void __exit idxd_exit_module(void)
|
{
|
idxd_unregister_driver();
|
pci_unregister_driver(&idxd_pci_driver);
|
idxd_cdev_remove();
|
idxd_unregister_bus_type();
|
}
|
module_exit(idxd_exit_module);
|
