/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Header file for the Atmel AHB DMA Controller driver
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*
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* Copyright (C) 2008 Atmel Corporation
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*/
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#ifndef AT_HDMAC_REGS_H
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#define AT_HDMAC_REGS_H
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#include <linux/platform_data/dma-atmel.h>
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#define AT_DMA_MAX_NR_CHANNELS 8
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#define AT_DMA_GCFG 0x00 /* Global Configuration Register */
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#define AT_DMA_IF_BIGEND(i) (0x1 << (i)) /* AHB-Lite Interface i in Big-endian mode */
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#define AT_DMA_ARB_CFG (0x1 << 4) /* Arbiter mode. */
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#define AT_DMA_ARB_CFG_FIXED (0x0 << 4)
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#define AT_DMA_ARB_CFG_ROUND_ROBIN (0x1 << 4)
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#define AT_DMA_EN 0x04 /* Controller Enable Register */
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#define AT_DMA_ENABLE (0x1 << 0)
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#define AT_DMA_SREQ 0x08 /* Software Single Request Register */
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#define AT_DMA_SSREQ(x) (0x1 << ((x) << 1)) /* Request a source single transfer on channel x */
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#define AT_DMA_DSREQ(x) (0x1 << (1 + ((x) << 1))) /* Request a destination single transfer on channel x */
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#define AT_DMA_CREQ 0x0C /* Software Chunk Transfer Request Register */
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#define AT_DMA_SCREQ(x) (0x1 << ((x) << 1)) /* Request a source chunk transfer on channel x */
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#define AT_DMA_DCREQ(x) (0x1 << (1 + ((x) << 1))) /* Request a destination chunk transfer on channel x */
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#define AT_DMA_LAST 0x10 /* Software Last Transfer Flag Register */
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#define AT_DMA_SLAST(x) (0x1 << ((x) << 1)) /* This src rq is last tx of buffer on channel x */
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#define AT_DMA_DLAST(x) (0x1 << (1 + ((x) << 1))) /* This dst rq is last tx of buffer on channel x */
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#define AT_DMA_SYNC 0x14 /* Request Synchronization Register */
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#define AT_DMA_SYR(h) (0x1 << (h)) /* Synchronize handshake line h */
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/* Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt registers */
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#define AT_DMA_EBCIER 0x18 /* Enable register */
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#define AT_DMA_EBCIDR 0x1C /* Disable register */
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#define AT_DMA_EBCIMR 0x20 /* Mask Register */
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#define AT_DMA_EBCISR 0x24 /* Status Register */
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#define AT_DMA_CBTC_OFFSET 8
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#define AT_DMA_ERR_OFFSET 16
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#define AT_DMA_BTC(x) (0x1 << (x))
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#define AT_DMA_CBTC(x) (0x1 << (AT_DMA_CBTC_OFFSET + (x)))
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#define AT_DMA_ERR(x) (0x1 << (AT_DMA_ERR_OFFSET + (x)))
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#define AT_DMA_CHER 0x28 /* Channel Handler Enable Register */
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#define AT_DMA_ENA(x) (0x1 << (x))
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#define AT_DMA_SUSP(x) (0x1 << ( 8 + (x)))
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#define AT_DMA_KEEP(x) (0x1 << (24 + (x)))
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#define AT_DMA_CHDR 0x2C /* Channel Handler Disable Register */
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#define AT_DMA_DIS(x) (0x1 << (x))
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#define AT_DMA_RES(x) (0x1 << ( 8 + (x)))
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#define AT_DMA_CHSR 0x30 /* Channel Handler Status Register */
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#define AT_DMA_EMPT(x) (0x1 << (16 + (x)))
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#define AT_DMA_STAL(x) (0x1 << (24 + (x)))
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#define AT_DMA_CH_REGS_BASE 0x3C /* Channel registers base address */
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#define ch_regs(x) (AT_DMA_CH_REGS_BASE + (x) * 0x28) /* Channel x base addr */
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/* Hardware register offset for each channel */
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#define ATC_SADDR_OFFSET 0x00 /* Source Address Register */
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#define ATC_DADDR_OFFSET 0x04 /* Destination Address Register */
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#define ATC_DSCR_OFFSET 0x08 /* Descriptor Address Register */
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#define ATC_CTRLA_OFFSET 0x0C /* Control A Register */
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#define ATC_CTRLB_OFFSET 0x10 /* Control B Register */
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#define ATC_CFG_OFFSET 0x14 /* Configuration Register */
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#define ATC_SPIP_OFFSET 0x18 /* Src PIP Configuration Register */
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#define ATC_DPIP_OFFSET 0x1C /* Dst PIP Configuration Register */
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/* Bitfield definitions */
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/* Bitfields in DSCR */
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#define ATC_DSCR_IF(i) (0x3 & (i)) /* Dsc feched via AHB-Lite Interface i */
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/* Bitfields in CTRLA */
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#define ATC_BTSIZE_MAX 0xFFFFUL /* Maximum Buffer Transfer Size */
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#define ATC_BTSIZE(x) (ATC_BTSIZE_MAX & (x)) /* Buffer Transfer Size */
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#define ATC_SCSIZE_MASK (0x7 << 16) /* Source Chunk Transfer Size */
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#define ATC_SCSIZE(x) (ATC_SCSIZE_MASK & ((x) << 16))
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#define ATC_SCSIZE_1 (0x0 << 16)
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#define ATC_SCSIZE_4 (0x1 << 16)
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#define ATC_SCSIZE_8 (0x2 << 16)
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#define ATC_SCSIZE_16 (0x3 << 16)
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#define ATC_SCSIZE_32 (0x4 << 16)
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#define ATC_SCSIZE_64 (0x5 << 16)
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#define ATC_SCSIZE_128 (0x6 << 16)
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#define ATC_SCSIZE_256 (0x7 << 16)
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#define ATC_DCSIZE_MASK (0x7 << 20) /* Destination Chunk Transfer Size */
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#define ATC_DCSIZE(x) (ATC_DCSIZE_MASK & ((x) << 20))
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#define ATC_DCSIZE_1 (0x0 << 20)
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#define ATC_DCSIZE_4 (0x1 << 20)
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#define ATC_DCSIZE_8 (0x2 << 20)
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#define ATC_DCSIZE_16 (0x3 << 20)
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#define ATC_DCSIZE_32 (0x4 << 20)
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#define ATC_DCSIZE_64 (0x5 << 20)
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#define ATC_DCSIZE_128 (0x6 << 20)
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#define ATC_DCSIZE_256 (0x7 << 20)
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#define ATC_SRC_WIDTH_MASK (0x3 << 24) /* Source Single Transfer Size */
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#define ATC_SRC_WIDTH(x) ((x) << 24)
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#define ATC_SRC_WIDTH_BYTE (0x0 << 24)
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#define ATC_SRC_WIDTH_HALFWORD (0x1 << 24)
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#define ATC_SRC_WIDTH_WORD (0x2 << 24)
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#define ATC_REG_TO_SRC_WIDTH(r) (((r) >> 24) & 0x3)
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#define ATC_DST_WIDTH_MASK (0x3 << 28) /* Destination Single Transfer Size */
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#define ATC_DST_WIDTH(x) ((x) << 28)
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#define ATC_DST_WIDTH_BYTE (0x0 << 28)
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#define ATC_DST_WIDTH_HALFWORD (0x1 << 28)
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#define ATC_DST_WIDTH_WORD (0x2 << 28)
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#define ATC_DONE (0x1 << 31) /* Tx Done (only written back in descriptor) */
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/* Bitfields in CTRLB */
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#define ATC_SIF(i) (0x3 & (i)) /* Src tx done via AHB-Lite Interface i */
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#define ATC_DIF(i) ((0x3 & (i)) << 4) /* Dst tx done via AHB-Lite Interface i */
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/* Specify AHB interfaces */
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#define AT_DMA_MEM_IF 0 /* interface 0 as memory interface */
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#define AT_DMA_PER_IF 1 /* interface 1 as peripheral interface */
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#define ATC_SRC_PIP (0x1 << 8) /* Source Picture-in-Picture enabled */
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#define ATC_DST_PIP (0x1 << 12) /* Destination Picture-in-Picture enabled */
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#define ATC_SRC_DSCR_DIS (0x1 << 16) /* Src Descriptor fetch disable */
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#define ATC_DST_DSCR_DIS (0x1 << 20) /* Dst Descriptor fetch disable */
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#define ATC_FC_MASK (0x7 << 21) /* Choose Flow Controller */
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#define ATC_FC_MEM2MEM (0x0 << 21) /* Mem-to-Mem (DMA) */
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#define ATC_FC_MEM2PER (0x1 << 21) /* Mem-to-Periph (DMA) */
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#define ATC_FC_PER2MEM (0x2 << 21) /* Periph-to-Mem (DMA) */
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#define ATC_FC_PER2PER (0x3 << 21) /* Periph-to-Periph (DMA) */
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#define ATC_FC_PER2MEM_PER (0x4 << 21) /* Periph-to-Mem (Peripheral) */
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#define ATC_FC_MEM2PER_PER (0x5 << 21) /* Mem-to-Periph (Peripheral) */
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#define ATC_FC_PER2PER_SRCPER (0x6 << 21) /* Periph-to-Periph (Src Peripheral) */
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#define ATC_FC_PER2PER_DSTPER (0x7 << 21) /* Periph-to-Periph (Dst Peripheral) */
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#define ATC_SRC_ADDR_MODE_MASK (0x3 << 24)
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#define ATC_SRC_ADDR_MODE_INCR (0x0 << 24) /* Incrementing Mode */
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#define ATC_SRC_ADDR_MODE_DECR (0x1 << 24) /* Decrementing Mode */
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#define ATC_SRC_ADDR_MODE_FIXED (0x2 << 24) /* Fixed Mode */
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#define ATC_DST_ADDR_MODE_MASK (0x3 << 28)
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#define ATC_DST_ADDR_MODE_INCR (0x0 << 28) /* Incrementing Mode */
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#define ATC_DST_ADDR_MODE_DECR (0x1 << 28) /* Decrementing Mode */
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#define ATC_DST_ADDR_MODE_FIXED (0x2 << 28) /* Fixed Mode */
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#define ATC_IEN (0x1 << 30) /* BTC interrupt enable (active low) */
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#define ATC_AUTO (0x1 << 31) /* Auto multiple buffer tx enable */
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/* Bitfields in CFG */
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/* are in at_hdmac.h */
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/* Bitfields in SPIP */
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#define ATC_SPIP_HOLE(x) (0xFFFFU & (x))
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#define ATC_SPIP_BOUNDARY(x) ((0x3FF & (x)) << 16)
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/* Bitfields in DPIP */
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#define ATC_DPIP_HOLE(x) (0xFFFFU & (x))
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#define ATC_DPIP_BOUNDARY(x) ((0x3FF & (x)) << 16)
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/*-- descriptors -----------------------------------------------------*/
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/* LLI == Linked List Item; aka DMA buffer descriptor */
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struct at_lli {
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/* values that are not changed by hardware */
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u32 saddr;
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u32 daddr;
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/* value that may get written back: */
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u32 ctrla;
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/* more values that are not changed by hardware */
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u32 ctrlb;
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u32 dscr; /* chain to next lli */
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};
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/**
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* struct at_desc - software descriptor
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* @at_lli: hardware lli structure
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* @txd: support for the async_tx api
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* @desc_node: node on the channed descriptors list
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* @len: descriptor byte count
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* @total_len: total transaction byte count
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*/
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struct at_desc {
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/* FIRST values the hardware uses */
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struct at_lli lli;
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/* THEN values for driver housekeeping */
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struct list_head tx_list;
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struct dma_async_tx_descriptor txd;
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struct list_head desc_node;
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size_t len;
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size_t total_len;
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/* Interleaved data */
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size_t boundary;
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size_t dst_hole;
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size_t src_hole;
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/* Memset temporary buffer */
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bool memset_buffer;
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dma_addr_t memset_paddr;
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int *memset_vaddr;
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};
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static inline struct at_desc *
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txd_to_at_desc(struct dma_async_tx_descriptor *txd)
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{
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return container_of(txd, struct at_desc, txd);
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}
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/*-- Channels --------------------------------------------------------*/
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/**
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* atc_status - information bits stored in channel status flag
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*
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* Manipulated with atomic operations.
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*/
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enum atc_status {
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ATC_IS_ERROR = 0,
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ATC_IS_PAUSED = 1,
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ATC_IS_CYCLIC = 24,
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};
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/**
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* struct at_dma_chan - internal representation of an Atmel HDMAC channel
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* @chan_common: common dmaengine channel object members
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* @device: parent device
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* @ch_regs: memory mapped register base
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* @mask: channel index in a mask
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* @per_if: peripheral interface
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* @mem_if: memory interface
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* @status: transmit status information from irq/prep* functions
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* to tasklet (use atomic operations)
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* @tasklet: bottom half to finish transaction work
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* @save_cfg: configuration register that is saved on suspend/resume cycle
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* @save_dscr: for cyclic operations, preserve next descriptor address in
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* the cyclic list on suspend/resume cycle
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* @dma_sconfig: configuration for slave transfers, passed via
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* .device_config
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* @lock: serializes enqueue/dequeue operations to descriptors lists
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* @active_list: list of descriptors dmaengine is being running on
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* @queue: list of descriptors ready to be submitted to engine
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* @free_list: list of descriptors usable by the channel
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*/
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struct at_dma_chan {
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struct dma_chan chan_common;
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struct at_dma *device;
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void __iomem *ch_regs;
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u8 mask;
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u8 per_if;
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u8 mem_if;
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unsigned long status;
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struct tasklet_struct tasklet;
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u32 save_cfg;
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u32 save_dscr;
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struct dma_slave_config dma_sconfig;
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spinlock_t lock;
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/* these other elements are all protected by lock */
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struct list_head active_list;
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struct list_head queue;
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struct list_head free_list;
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};
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#define channel_readl(atchan, name) \
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__raw_readl((atchan)->ch_regs + ATC_##name##_OFFSET)
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#define channel_writel(atchan, name, val) \
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__raw_writel((val), (atchan)->ch_regs + ATC_##name##_OFFSET)
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static inline struct at_dma_chan *to_at_dma_chan(struct dma_chan *dchan)
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{
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return container_of(dchan, struct at_dma_chan, chan_common);
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}
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/*
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* Fix sconfig's burst size according to at_hdmac. We need to convert them as:
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* 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3, 32 -> 4, 64 -> 5, 128 -> 6, 256 -> 7.
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*
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* This can be done by finding most significant bit set.
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*/
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static inline void convert_burst(u32 *maxburst)
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{
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if (*maxburst > 1)
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*maxburst = fls(*maxburst) - 2;
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else
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*maxburst = 0;
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}
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/*
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* Fix sconfig's bus width according to at_hdmac.
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* 1 byte -> 0, 2 bytes -> 1, 4 bytes -> 2.
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*/
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static inline u8 convert_buswidth(enum dma_slave_buswidth addr_width)
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{
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switch (addr_width) {
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case DMA_SLAVE_BUSWIDTH_2_BYTES:
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return 1;
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case DMA_SLAVE_BUSWIDTH_4_BYTES:
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return 2;
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default:
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/* For 1 byte width or fallback */
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return 0;
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}
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}
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/*-- Controller ------------------------------------------------------*/
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/**
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* struct at_dma - internal representation of an Atmel HDMA Controller
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* @chan_common: common dmaengine dma_device object members
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* @atdma_devtype: identifier of DMA controller compatibility
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* @ch_regs: memory mapped register base
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* @clk: dma controller clock
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* @save_imr: interrupt mask register that is saved on suspend/resume cycle
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* @all_chan_mask: all channels availlable in a mask
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* @dma_desc_pool: base of DMA descriptor region (DMA address)
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* @chan: channels table to store at_dma_chan structures
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*/
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struct at_dma {
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struct dma_device dma_common;
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void __iomem *regs;
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struct clk *clk;
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u32 save_imr;
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u8 all_chan_mask;
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struct dma_pool *dma_desc_pool;
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struct dma_pool *memset_pool;
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/* AT THE END channels table */
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struct at_dma_chan chan[];
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};
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#define dma_readl(atdma, name) \
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__raw_readl((atdma)->regs + AT_DMA_##name)
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#define dma_writel(atdma, name, val) \
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__raw_writel((val), (atdma)->regs + AT_DMA_##name)
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static inline struct at_dma *to_at_dma(struct dma_device *ddev)
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{
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return container_of(ddev, struct at_dma, dma_common);
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}
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/*-- Helper functions ------------------------------------------------*/
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static struct device *chan2dev(struct dma_chan *chan)
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{
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return &chan->dev->device;
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}
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#if defined(VERBOSE_DEBUG)
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static void vdbg_dump_regs(struct at_dma_chan *atchan)
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{
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struct at_dma *atdma = to_at_dma(atchan->chan_common.device);
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dev_err(chan2dev(&atchan->chan_common),
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" channel %d : imr = 0x%x, chsr = 0x%x\n",
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atchan->chan_common.chan_id,
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dma_readl(atdma, EBCIMR),
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dma_readl(atdma, CHSR));
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dev_err(chan2dev(&atchan->chan_common),
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" channel: s0x%x d0x%x ctrl0x%x:0x%x cfg0x%x l0x%x\n",
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channel_readl(atchan, SADDR),
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channel_readl(atchan, DADDR),
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channel_readl(atchan, CTRLA),
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channel_readl(atchan, CTRLB),
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channel_readl(atchan, CFG),
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channel_readl(atchan, DSCR));
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}
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#else
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static void vdbg_dump_regs(struct at_dma_chan *atchan) {}
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#endif
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static void atc_dump_lli(struct at_dma_chan *atchan, struct at_lli *lli)
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{
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dev_crit(chan2dev(&atchan->chan_common),
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"desc: s%pad d%pad ctrl0x%x:0x%x l%pad\n",
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&lli->saddr, &lli->daddr,
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lli->ctrla, lli->ctrlb, &lli->dscr);
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}
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static void atc_setup_irq(struct at_dma *atdma, int chan_id, int on)
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{
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u32 ebci;
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/* enable interrupts on buffer transfer completion & error */
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ebci = AT_DMA_BTC(chan_id)
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| AT_DMA_ERR(chan_id);
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if (on)
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dma_writel(atdma, EBCIER, ebci);
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else
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dma_writel(atdma, EBCIDR, ebci);
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}
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static void atc_enable_chan_irq(struct at_dma *atdma, int chan_id)
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{
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atc_setup_irq(atdma, chan_id, 1);
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}
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static void atc_disable_chan_irq(struct at_dma *atdma, int chan_id)
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{
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atc_setup_irq(atdma, chan_id, 0);
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}
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/**
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* atc_chan_is_enabled - test if given channel is enabled
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* @atchan: channel we want to test status
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*/
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static inline int atc_chan_is_enabled(struct at_dma_chan *atchan)
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{
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struct at_dma *atdma = to_at_dma(atchan->chan_common.device);
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return !!(dma_readl(atdma, CHSR) & atchan->mask);
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}
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/**
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* atc_chan_is_paused - test channel pause/resume status
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* @atchan: channel we want to test status
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*/
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static inline int atc_chan_is_paused(struct at_dma_chan *atchan)
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{
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return test_bit(ATC_IS_PAUSED, &atchan->status);
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}
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/**
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* atc_chan_is_cyclic - test if given channel has cyclic property set
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* @atchan: channel we want to test status
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*/
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static inline int atc_chan_is_cyclic(struct at_dma_chan *atchan)
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{
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return test_bit(ATC_IS_CYCLIC, &atchan->status);
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}
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/**
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* set_desc_eol - set end-of-link to descriptor so it will end transfer
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* @desc: descriptor, signle or at the end of a chain, to end chain on
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*/
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static void set_desc_eol(struct at_desc *desc)
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{
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u32 ctrlb = desc->lli.ctrlb;
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ctrlb &= ~ATC_IEN;
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ctrlb |= ATC_SRC_DSCR_DIS | ATC_DST_DSCR_DIS;
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desc->lli.ctrlb = ctrlb;
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desc->lli.dscr = 0;
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}
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#endif /* AT_HDMAC_REGS_H */
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