// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018-2019 SiFive, Inc.
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* Wesley Terpstra
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* The FU540 PRCI implements clock and reset control for the SiFive
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* FU540-C000 chip. This driver assumes that it has sole control
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* over all PRCI resources.
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*
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* This driver is based on the PRCI driver written by Wesley Terpstra:
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* https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b2ee56bb60
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*
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* References:
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* - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset"
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*/
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#include <dt-bindings/clock/sifive-fu540-prci.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/clk/analogbits-wrpll-cln28hpc.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_clk.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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/*
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* EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects:
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* hfclk and rtcclk
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*/
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#define EXPECTED_CLK_PARENT_COUNT 2
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/*
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* Register offsets and bitmasks
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*/
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/* COREPLLCFG0 */
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#define PRCI_COREPLLCFG0_OFFSET 0x4
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# define PRCI_COREPLLCFG0_DIVR_SHIFT 0
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# define PRCI_COREPLLCFG0_DIVR_MASK (0x3f << PRCI_COREPLLCFG0_DIVR_SHIFT)
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# define PRCI_COREPLLCFG0_DIVF_SHIFT 6
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# define PRCI_COREPLLCFG0_DIVF_MASK (0x1ff << PRCI_COREPLLCFG0_DIVF_SHIFT)
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# define PRCI_COREPLLCFG0_DIVQ_SHIFT 15
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# define PRCI_COREPLLCFG0_DIVQ_MASK (0x7 << PRCI_COREPLLCFG0_DIVQ_SHIFT)
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# define PRCI_COREPLLCFG0_RANGE_SHIFT 18
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# define PRCI_COREPLLCFG0_RANGE_MASK (0x7 << PRCI_COREPLLCFG0_RANGE_SHIFT)
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# define PRCI_COREPLLCFG0_BYPASS_SHIFT 24
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# define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 << PRCI_COREPLLCFG0_BYPASS_SHIFT)
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# define PRCI_COREPLLCFG0_FSE_SHIFT 25
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# define PRCI_COREPLLCFG0_FSE_MASK (0x1 << PRCI_COREPLLCFG0_FSE_SHIFT)
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# define PRCI_COREPLLCFG0_LOCK_SHIFT 31
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# define PRCI_COREPLLCFG0_LOCK_MASK (0x1 << PRCI_COREPLLCFG0_LOCK_SHIFT)
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/* DDRPLLCFG0 */
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#define PRCI_DDRPLLCFG0_OFFSET 0xc
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# define PRCI_DDRPLLCFG0_DIVR_SHIFT 0
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# define PRCI_DDRPLLCFG0_DIVR_MASK (0x3f << PRCI_DDRPLLCFG0_DIVR_SHIFT)
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# define PRCI_DDRPLLCFG0_DIVF_SHIFT 6
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# define PRCI_DDRPLLCFG0_DIVF_MASK (0x1ff << PRCI_DDRPLLCFG0_DIVF_SHIFT)
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# define PRCI_DDRPLLCFG0_DIVQ_SHIFT 15
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# define PRCI_DDRPLLCFG0_DIVQ_MASK (0x7 << PRCI_DDRPLLCFG0_DIVQ_SHIFT)
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# define PRCI_DDRPLLCFG0_RANGE_SHIFT 18
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# define PRCI_DDRPLLCFG0_RANGE_MASK (0x7 << PRCI_DDRPLLCFG0_RANGE_SHIFT)
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# define PRCI_DDRPLLCFG0_BYPASS_SHIFT 24
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# define PRCI_DDRPLLCFG0_BYPASS_MASK (0x1 << PRCI_DDRPLLCFG0_BYPASS_SHIFT)
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# define PRCI_DDRPLLCFG0_FSE_SHIFT 25
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# define PRCI_DDRPLLCFG0_FSE_MASK (0x1 << PRCI_DDRPLLCFG0_FSE_SHIFT)
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# define PRCI_DDRPLLCFG0_LOCK_SHIFT 31
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# define PRCI_DDRPLLCFG0_LOCK_MASK (0x1 << PRCI_DDRPLLCFG0_LOCK_SHIFT)
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/* DDRPLLCFG1 */
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#define PRCI_DDRPLLCFG1_OFFSET 0x10
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# define PRCI_DDRPLLCFG1_CKE_SHIFT 24
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# define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT)
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/* GEMGXLPLLCFG0 */
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#define PRCI_GEMGXLPLLCFG0_OFFSET 0x1c
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# define PRCI_GEMGXLPLLCFG0_DIVR_SHIFT 0
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# define PRCI_GEMGXLPLLCFG0_DIVR_MASK (0x3f << PRCI_GEMGXLPLLCFG0_DIVR_SHIFT)
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# define PRCI_GEMGXLPLLCFG0_DIVF_SHIFT 6
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# define PRCI_GEMGXLPLLCFG0_DIVF_MASK (0x1ff << PRCI_GEMGXLPLLCFG0_DIVF_SHIFT)
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# define PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT 15
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# define PRCI_GEMGXLPLLCFG0_DIVQ_MASK (0x7 << PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT)
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# define PRCI_GEMGXLPLLCFG0_RANGE_SHIFT 18
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# define PRCI_GEMGXLPLLCFG0_RANGE_MASK (0x7 << PRCI_GEMGXLPLLCFG0_RANGE_SHIFT)
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# define PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT 24
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# define PRCI_GEMGXLPLLCFG0_BYPASS_MASK (0x1 << PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT)
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# define PRCI_GEMGXLPLLCFG0_FSE_SHIFT 25
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# define PRCI_GEMGXLPLLCFG0_FSE_MASK (0x1 << PRCI_GEMGXLPLLCFG0_FSE_SHIFT)
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# define PRCI_GEMGXLPLLCFG0_LOCK_SHIFT 31
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# define PRCI_GEMGXLPLLCFG0_LOCK_MASK (0x1 << PRCI_GEMGXLPLLCFG0_LOCK_SHIFT)
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/* GEMGXLPLLCFG1 */
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#define PRCI_GEMGXLPLLCFG1_OFFSET 0x20
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# define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 24
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# define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT)
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/* CORECLKSEL */
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#define PRCI_CORECLKSEL_OFFSET 0x24
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# define PRCI_CORECLKSEL_CORECLKSEL_SHIFT 0
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# define PRCI_CORECLKSEL_CORECLKSEL_MASK (0x1 << PRCI_CORECLKSEL_CORECLKSEL_SHIFT)
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/* DEVICESRESETREG */
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#define PRCI_DEVICESRESETREG_OFFSET 0x28
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# define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT 0
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# define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK (0x1 << PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT)
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# define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT 1
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# define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_MASK (0x1 << PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT)
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# define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT 2
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# define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_MASK (0x1 << PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT)
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# define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT 3
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# define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_MASK (0x1 << PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT)
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# define PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT 5
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# define PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK (0x1 << PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT)
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/* CLKMUXSTATUSREG */
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#define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c
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# define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1
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# define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK (0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT)
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/*
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* Private structures
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*/
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/**
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* struct __prci_data - per-device-instance data
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* @va: base virtual address of the PRCI IP block
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* @hw_clks: encapsulates struct clk_hw records
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*
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* PRCI per-device instance data
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*/
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struct __prci_data {
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void __iomem *va;
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struct clk_hw_onecell_data hw_clks;
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};
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/**
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* struct __prci_wrpll_data - WRPLL configuration and integration data
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* @c: WRPLL current configuration record
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* @enable_bypass: fn ptr to code to bypass the WRPLL (if applicable; else NULL)
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* @disable_bypass: fn ptr to code to not bypass the WRPLL (or NULL)
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* @cfg0_offs: WRPLL CFG0 register offset (in bytes) from the PRCI base address
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*
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* @enable_bypass and @disable_bypass are used for WRPLL instances
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* that contain a separate external glitchless clock mux downstream
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* from the PLL. The WRPLL internal bypass mux is not glitchless.
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*/
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struct __prci_wrpll_data {
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struct wrpll_cfg c;
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void (*enable_bypass)(struct __prci_data *pd);
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void (*disable_bypass)(struct __prci_data *pd);
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u8 cfg0_offs;
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};
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/**
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* struct __prci_clock - describes a clock device managed by PRCI
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* @name: user-readable clock name string - should match the manual
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* @parent_name: parent name for this clock
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* @ops: struct clk_ops for the Linux clock framework to use for control
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* @hw: Linux-private clock data
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* @pwd: WRPLL-specific data, associated with this clock (if not NULL)
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* @pd: PRCI-specific data associated with this clock (if not NULL)
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*
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* PRCI clock data. Used by the PRCI driver to register PRCI-provided
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* clocks to the Linux clock infrastructure.
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*/
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struct __prci_clock {
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const char *name;
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const char *parent_name;
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const struct clk_ops *ops;
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struct clk_hw hw;
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struct __prci_wrpll_data *pwd;
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struct __prci_data *pd;
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};
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#define clk_hw_to_prci_clock(pwd) container_of(pwd, struct __prci_clock, hw)
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/*
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* Private functions
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*/
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/**
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* __prci_readl() - read from a PRCI register
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* @pd: PRCI context
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* @offs: register offset to read from (in bytes, from PRCI base address)
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*
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* Read the register located at offset @offs from the base virtual
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* address of the PRCI register target described by @pd, and return
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* the value to the caller.
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*
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* Context: Any context.
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*
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* Return: the contents of the register described by @pd and @offs.
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*/
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static u32 __prci_readl(struct __prci_data *pd, u32 offs)
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{
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return readl_relaxed(pd->va + offs);
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}
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static void __prci_writel(u32 v, u32 offs, struct __prci_data *pd)
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{
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writel_relaxed(v, pd->va + offs);
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}
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/* WRPLL-related private functions */
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/**
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* __prci_wrpll_unpack() - unpack WRPLL configuration registers into parameters
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* @c: ptr to a struct wrpll_cfg record to write config into
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* @r: value read from the PRCI PLL configuration register
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*
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* Given a value @r read from an FU540 PRCI PLL configuration register,
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* split it into fields and populate it into the WRPLL configuration record
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* pointed to by @c.
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*
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* The COREPLLCFG0 macros are used below, but the other *PLLCFG0 macros
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* have the same register layout.
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*
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* Context: Any context.
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*/
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static void __prci_wrpll_unpack(struct wrpll_cfg *c, u32 r)
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{
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u32 v;
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v = r & PRCI_COREPLLCFG0_DIVR_MASK;
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v >>= PRCI_COREPLLCFG0_DIVR_SHIFT;
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c->divr = v;
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v = r & PRCI_COREPLLCFG0_DIVF_MASK;
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v >>= PRCI_COREPLLCFG0_DIVF_SHIFT;
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c->divf = v;
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v = r & PRCI_COREPLLCFG0_DIVQ_MASK;
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v >>= PRCI_COREPLLCFG0_DIVQ_SHIFT;
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c->divq = v;
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v = r & PRCI_COREPLLCFG0_RANGE_MASK;
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v >>= PRCI_COREPLLCFG0_RANGE_SHIFT;
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c->range = v;
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c->flags &= (WRPLL_FLAGS_INT_FEEDBACK_MASK |
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WRPLL_FLAGS_EXT_FEEDBACK_MASK);
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/* external feedback mode not supported */
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c->flags |= WRPLL_FLAGS_INT_FEEDBACK_MASK;
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}
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/**
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* __prci_wrpll_pack() - pack PLL configuration parameters into a register value
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* @c: pointer to a struct wrpll_cfg record containing the PLL's cfg
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*
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* Using a set of WRPLL configuration values pointed to by @c,
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* assemble a PRCI PLL configuration register value, and return it to
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* the caller.
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*
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* Context: Any context. Caller must ensure that the contents of the
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* record pointed to by @c do not change during the execution
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* of this function.
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*
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* Returns: a value suitable for writing into a PRCI PLL configuration
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* register
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*/
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static u32 __prci_wrpll_pack(const struct wrpll_cfg *c)
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{
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u32 r = 0;
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r |= c->divr << PRCI_COREPLLCFG0_DIVR_SHIFT;
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r |= c->divf << PRCI_COREPLLCFG0_DIVF_SHIFT;
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r |= c->divq << PRCI_COREPLLCFG0_DIVQ_SHIFT;
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r |= c->range << PRCI_COREPLLCFG0_RANGE_SHIFT;
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/* external feedback mode not supported */
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r |= PRCI_COREPLLCFG0_FSE_MASK;
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return r;
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}
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/**
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* __prci_wrpll_read_cfg() - read the WRPLL configuration from the PRCI
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* @pd: PRCI context
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* @pwd: PRCI WRPLL metadata
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*
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* Read the current configuration of the PLL identified by @pwd from
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* the PRCI identified by @pd, and store it into the local configuration
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* cache in @pwd.
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*
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* Context: Any context. Caller must prevent the records pointed to by
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* @pd and @pwd from changing during execution.
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*/
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static void __prci_wrpll_read_cfg(struct __prci_data *pd,
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struct __prci_wrpll_data *pwd)
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{
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__prci_wrpll_unpack(&pwd->c, __prci_readl(pd, pwd->cfg0_offs));
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}
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/**
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* __prci_wrpll_write_cfg() - write WRPLL configuration into the PRCI
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* @pd: PRCI context
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* @pwd: PRCI WRPLL metadata
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* @c: WRPLL configuration record to write
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*
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* Write the WRPLL configuration described by @c into the WRPLL
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* configuration register identified by @pwd in the PRCI instance
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* described by @c. Make a cached copy of the WRPLL's current
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* configuration so it can be used by other code.
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*
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* Context: Any context. Caller must prevent the records pointed to by
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* @pd and @pwd from changing during execution.
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*/
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static void __prci_wrpll_write_cfg(struct __prci_data *pd,
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struct __prci_wrpll_data *pwd,
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struct wrpll_cfg *c)
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{
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__prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd);
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memcpy(&pwd->c, c, sizeof(*c));
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}
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/* Core clock mux control */
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/**
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* __prci_coreclksel_use_hfclk() - switch the CORECLK mux to output HFCLK
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* @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
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*
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* Switch the CORECLK mux to the HFCLK input source; return once complete.
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*
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* Context: Any context. Caller must prevent concurrent changes to the
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* PRCI_CORECLKSEL_OFFSET register.
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*/
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static void __prci_coreclksel_use_hfclk(struct __prci_data *pd)
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{
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u32 r;
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r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);
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r |= PRCI_CORECLKSEL_CORECLKSEL_MASK;
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__prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);
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r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */
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}
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/**
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* __prci_coreclksel_use_corepll() - switch the CORECLK mux to output COREPLL
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* @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
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*
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* Switch the CORECLK mux to the PLL output clock; return once complete.
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*
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* Context: Any context. Caller must prevent concurrent changes to the
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* PRCI_CORECLKSEL_OFFSET register.
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*/
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static void __prci_coreclksel_use_corepll(struct __prci_data *pd)
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{
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u32 r;
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r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);
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r &= ~PRCI_CORECLKSEL_CORECLKSEL_MASK;
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__prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);
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r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */
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}
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/*
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* Linux clock framework integration
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*
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* See the Linux clock framework documentation for more information on
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* these functions.
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*/
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static unsigned long sifive_fu540_prci_wrpll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
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struct __prci_wrpll_data *pwd = pc->pwd;
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return wrpll_calc_output_rate(&pwd->c, parent_rate);
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}
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static long sifive_fu540_prci_wrpll_round_rate(struct clk_hw *hw,
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unsigned long rate,
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unsigned long *parent_rate)
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{
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struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
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struct __prci_wrpll_data *pwd = pc->pwd;
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struct wrpll_cfg c;
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memcpy(&c, &pwd->c, sizeof(c));
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wrpll_configure_for_rate(&c, rate, *parent_rate);
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return wrpll_calc_output_rate(&c, *parent_rate);
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}
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static int sifive_fu540_prci_wrpll_set_rate(struct clk_hw *hw,
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unsigned long rate,
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unsigned long parent_rate)
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{
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struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
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struct __prci_wrpll_data *pwd = pc->pwd;
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struct __prci_data *pd = pc->pd;
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int r;
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r = wrpll_configure_for_rate(&pwd->c, rate, parent_rate);
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if (r)
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return r;
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if (pwd->enable_bypass)
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pwd->enable_bypass(pd);
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__prci_wrpll_write_cfg(pd, pwd, &pwd->c);
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udelay(wrpll_calc_max_lock_us(&pwd->c));
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if (pwd->disable_bypass)
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pwd->disable_bypass(pd);
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return 0;
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}
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static const struct clk_ops sifive_fu540_prci_wrpll_clk_ops = {
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.set_rate = sifive_fu540_prci_wrpll_set_rate,
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.round_rate = sifive_fu540_prci_wrpll_round_rate,
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.recalc_rate = sifive_fu540_prci_wrpll_recalc_rate,
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};
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static const struct clk_ops sifive_fu540_prci_wrpll_ro_clk_ops = {
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.recalc_rate = sifive_fu540_prci_wrpll_recalc_rate,
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};
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/* TLCLKSEL clock integration */
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static unsigned long sifive_fu540_prci_tlclksel_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
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struct __prci_data *pd = pc->pd;
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u32 v;
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u8 div;
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v = __prci_readl(pd, PRCI_CLKMUXSTATUSREG_OFFSET);
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v &= PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK;
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div = v ? 1 : 2;
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return div_u64(parent_rate, div);
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}
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static const struct clk_ops sifive_fu540_prci_tlclksel_clk_ops = {
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.recalc_rate = sifive_fu540_prci_tlclksel_recalc_rate,
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};
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/*
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* PRCI integration data for each WRPLL instance
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*/
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static struct __prci_wrpll_data __prci_corepll_data = {
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.cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
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.enable_bypass = __prci_coreclksel_use_hfclk,
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.disable_bypass = __prci_coreclksel_use_corepll,
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};
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static struct __prci_wrpll_data __prci_ddrpll_data = {
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.cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
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};
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static struct __prci_wrpll_data __prci_gemgxlpll_data = {
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.cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
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};
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/*
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* List of clock controls provided by the PRCI
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*/
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static struct __prci_clock __prci_init_clocks[] = {
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[PRCI_CLK_COREPLL] = {
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.name = "corepll",
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.parent_name = "hfclk",
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.ops = &sifive_fu540_prci_wrpll_clk_ops,
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.pwd = &__prci_corepll_data,
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},
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[PRCI_CLK_DDRPLL] = {
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.name = "ddrpll",
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.parent_name = "hfclk",
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.ops = &sifive_fu540_prci_wrpll_ro_clk_ops,
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.pwd = &__prci_ddrpll_data,
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},
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[PRCI_CLK_GEMGXLPLL] = {
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.name = "gemgxlpll",
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.parent_name = "hfclk",
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.ops = &sifive_fu540_prci_wrpll_clk_ops,
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.pwd = &__prci_gemgxlpll_data,
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},
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[PRCI_CLK_TLCLK] = {
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.name = "tlclk",
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.parent_name = "corepll",
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.ops = &sifive_fu540_prci_tlclksel_clk_ops,
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},
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};
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/**
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* __prci_register_clocks() - register clock controls in the PRCI with Linux
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* @dev: Linux struct device *
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*
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* Register the list of clock controls described in __prci_init_plls[] with
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* the Linux clock framework.
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*
|
* Return: 0 upon success or a negative error code upon failure.
|
*/
|
static int __prci_register_clocks(struct device *dev, struct __prci_data *pd)
|
{
|
struct clk_init_data init = { };
|
struct __prci_clock *pic;
|
int parent_count, i, r;
|
|
parent_count = of_clk_get_parent_count(dev->of_node);
|
if (parent_count != EXPECTED_CLK_PARENT_COUNT) {
|
dev_err(dev, "expected only two parent clocks, found %d\n",
|
parent_count);
|
return -EINVAL;
|
}
|
|
/* Register PLLs */
|
for (i = 0; i < ARRAY_SIZE(__prci_init_clocks); ++i) {
|
pic = &__prci_init_clocks[i];
|
|
init.name = pic->name;
|
init.parent_names = &pic->parent_name;
|
init.num_parents = 1;
|
init.ops = pic->ops;
|
pic->hw.init = &init;
|
|
pic->pd = pd;
|
|
if (pic->pwd)
|
__prci_wrpll_read_cfg(pd, pic->pwd);
|
|
r = devm_clk_hw_register(dev, &pic->hw);
|
if (r) {
|
dev_warn(dev, "Failed to register clock %s: %d\n",
|
init.name, r);
|
return r;
|
}
|
|
r = clk_hw_register_clkdev(&pic->hw, pic->name, dev_name(dev));
|
if (r) {
|
dev_warn(dev, "Failed to register clkdev for %s: %d\n",
|
init.name, r);
|
return r;
|
}
|
|
pd->hw_clks.hws[i] = &pic->hw;
|
}
|
|
pd->hw_clks.num = i;
|
|
r = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
|
&pd->hw_clks);
|
if (r) {
|
dev_err(dev, "could not add hw_provider: %d\n", r);
|
return r;
|
}
|
|
return 0;
|
}
|
|
/*
|
* Linux device model integration
|
*
|
* See the Linux device model documentation for more information about
|
* these functions.
|
*/
|
static int sifive_fu540_prci_probe(struct platform_device *pdev)
|
{
|
struct device *dev = &pdev->dev;
|
struct resource *res;
|
struct __prci_data *pd;
|
int r;
|
|
pd = devm_kzalloc(dev,
|
struct_size(pd, hw_clks.hws,
|
ARRAY_SIZE(__prci_init_clocks)),
|
GFP_KERNEL);
|
if (!pd)
|
return -ENOMEM;
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
pd->va = devm_ioremap_resource(dev, res);
|
if (IS_ERR(pd->va))
|
return PTR_ERR(pd->va);
|
|
r = __prci_register_clocks(dev, pd);
|
if (r) {
|
dev_err(dev, "could not register clocks: %d\n", r);
|
return r;
|
}
|
|
dev_dbg(dev, "SiFive FU540 PRCI probed\n");
|
|
return 0;
|
}
|
|
static const struct of_device_id sifive_fu540_prci_of_match[] = {
|
{ .compatible = "sifive,fu540-c000-prci", },
|
{}
|
};
|
MODULE_DEVICE_TABLE(of, sifive_fu540_prci_of_match);
|
|
static struct platform_driver sifive_fu540_prci_driver = {
|
.driver = {
|
.name = "sifive-fu540-prci",
|
.of_match_table = sifive_fu540_prci_of_match,
|
},
|
.probe = sifive_fu540_prci_probe,
|
};
|
|
static int __init sifive_fu540_prci_init(void)
|
{
|
return platform_driver_register(&sifive_fu540_prci_driver);
|
}
|
core_initcall(sifive_fu540_prci_init);
|
