// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* RNG driver for Freescale RNGC
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*
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* Copyright (C) 2008-2012 Freescale Semiconductor, Inc.
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* Copyright (C) 2017 Martin Kaiser <martin@kaiser.cx>
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*/
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/hw_random.h>
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#include <linux/completion.h>
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#include <linux/io.h>
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#define RNGC_VER_ID 0x0000
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#define RNGC_COMMAND 0x0004
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#define RNGC_CONTROL 0x0008
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#define RNGC_STATUS 0x000C
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#define RNGC_ERROR 0x0010
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#define RNGC_FIFO 0x0014
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/* the fields in the ver id register */
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#define RNGC_TYPE_SHIFT 28
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#define RNGC_VER_MAJ_SHIFT 8
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/* the rng_type field */
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#define RNGC_TYPE_RNGB 0x1
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#define RNGC_TYPE_RNGC 0x2
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#define RNGC_CMD_CLR_ERR 0x00000020
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#define RNGC_CMD_CLR_INT 0x00000010
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#define RNGC_CMD_SEED 0x00000002
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#define RNGC_CMD_SELF_TEST 0x00000001
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#define RNGC_CTRL_MASK_ERROR 0x00000040
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#define RNGC_CTRL_MASK_DONE 0x00000020
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#define RNGC_CTRL_AUTO_SEED 0x00000010
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#define RNGC_STATUS_ERROR 0x00010000
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#define RNGC_STATUS_FIFO_LEVEL_MASK 0x00000f00
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#define RNGC_STATUS_FIFO_LEVEL_SHIFT 8
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#define RNGC_STATUS_SEED_DONE 0x00000020
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#define RNGC_STATUS_ST_DONE 0x00000010
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#define RNGC_ERROR_STATUS_STAT_ERR 0x00000008
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#define RNGC_TIMEOUT 3000 /* 3 sec */
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static bool self_test = true;
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module_param(self_test, bool, 0);
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struct imx_rngc {
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struct device *dev;
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struct clk *clk;
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void __iomem *base;
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struct hwrng rng;
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struct completion rng_op_done;
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/*
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* err_reg is written only by the irq handler and read only
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* when interrupts are masked, we need no spinlock
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*/
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u32 err_reg;
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};
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static inline void imx_rngc_irq_mask_clear(struct imx_rngc *rngc)
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{
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u32 ctrl, cmd;
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/* mask interrupts */
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ctrl = readl(rngc->base + RNGC_CONTROL);
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ctrl |= RNGC_CTRL_MASK_DONE | RNGC_CTRL_MASK_ERROR;
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writel(ctrl, rngc->base + RNGC_CONTROL);
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/*
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* CLR_INT clears the interrupt only if there's no error
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* CLR_ERR clear the interrupt and the error register if there
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* is an error
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*/
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cmd = readl(rngc->base + RNGC_COMMAND);
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cmd |= RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR;
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writel(cmd, rngc->base + RNGC_COMMAND);
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}
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static inline void imx_rngc_irq_unmask(struct imx_rngc *rngc)
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{
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u32 ctrl;
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ctrl = readl(rngc->base + RNGC_CONTROL);
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ctrl &= ~(RNGC_CTRL_MASK_DONE | RNGC_CTRL_MASK_ERROR);
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writel(ctrl, rngc->base + RNGC_CONTROL);
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}
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static int imx_rngc_self_test(struct imx_rngc *rngc)
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{
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u32 cmd;
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int ret;
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imx_rngc_irq_unmask(rngc);
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/* run self test */
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cmd = readl(rngc->base + RNGC_COMMAND);
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writel(cmd | RNGC_CMD_SELF_TEST, rngc->base + RNGC_COMMAND);
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ret = wait_for_completion_timeout(&rngc->rng_op_done, msecs_to_jiffies(RNGC_TIMEOUT));
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imx_rngc_irq_mask_clear(rngc);
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if (!ret)
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return -ETIMEDOUT;
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return rngc->err_reg ? -EIO : 0;
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}
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static int imx_rngc_read(struct hwrng *rng, void *data, size_t max, bool wait)
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{
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struct imx_rngc *rngc = container_of(rng, struct imx_rngc, rng);
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unsigned int status;
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unsigned int level;
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int retval = 0;
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while (max >= sizeof(u32)) {
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status = readl(rngc->base + RNGC_STATUS);
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/* is there some error while reading this random number? */
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if (status & RNGC_STATUS_ERROR)
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break;
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/* how many random numbers are in FIFO? [0-16] */
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level = (status & RNGC_STATUS_FIFO_LEVEL_MASK) >>
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RNGC_STATUS_FIFO_LEVEL_SHIFT;
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if (level) {
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/* retrieve a random number from FIFO */
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*(u32 *)data = readl(rngc->base + RNGC_FIFO);
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retval += sizeof(u32);
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data += sizeof(u32);
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max -= sizeof(u32);
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}
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}
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return retval ? retval : -EIO;
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}
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static irqreturn_t imx_rngc_irq(int irq, void *priv)
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{
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struct imx_rngc *rngc = (struct imx_rngc *)priv;
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u32 status;
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/*
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* clearing the interrupt will also clear the error register
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* read error and status before clearing
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*/
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status = readl(rngc->base + RNGC_STATUS);
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rngc->err_reg = readl(rngc->base + RNGC_ERROR);
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imx_rngc_irq_mask_clear(rngc);
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if (status & (RNGC_STATUS_SEED_DONE | RNGC_STATUS_ST_DONE))
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complete(&rngc->rng_op_done);
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return IRQ_HANDLED;
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}
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static int imx_rngc_init(struct hwrng *rng)
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{
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struct imx_rngc *rngc = container_of(rng, struct imx_rngc, rng);
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u32 cmd, ctrl;
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int ret;
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/* clear error */
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cmd = readl(rngc->base + RNGC_COMMAND);
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writel(cmd | RNGC_CMD_CLR_ERR, rngc->base + RNGC_COMMAND);
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imx_rngc_irq_unmask(rngc);
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/* create seed, repeat while there is some statistical error */
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do {
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/* seed creation */
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cmd = readl(rngc->base + RNGC_COMMAND);
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writel(cmd | RNGC_CMD_SEED, rngc->base + RNGC_COMMAND);
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ret = wait_for_completion_timeout(&rngc->rng_op_done, msecs_to_jiffies(RNGC_TIMEOUT));
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if (!ret) {
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ret = -ETIMEDOUT;
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goto err;
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}
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} while (rngc->err_reg == RNGC_ERROR_STATUS_STAT_ERR);
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if (rngc->err_reg) {
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ret = -EIO;
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goto err;
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}
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/*
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* enable automatic seeding, the rngc creates a new seed automatically
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* after serving 2^20 random 160-bit words
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*/
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ctrl = readl(rngc->base + RNGC_CONTROL);
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ctrl |= RNGC_CTRL_AUTO_SEED;
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writel(ctrl, rngc->base + RNGC_CONTROL);
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/*
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* if initialisation was successful, we keep the interrupt
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* unmasked until imx_rngc_cleanup is called
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* we mask the interrupt ourselves if we return an error
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*/
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return 0;
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err:
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imx_rngc_irq_mask_clear(rngc);
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return ret;
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}
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static void imx_rngc_cleanup(struct hwrng *rng)
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{
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struct imx_rngc *rngc = container_of(rng, struct imx_rngc, rng);
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imx_rngc_irq_mask_clear(rngc);
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}
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static int imx_rngc_probe(struct platform_device *pdev)
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{
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struct imx_rngc *rngc;
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int ret;
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int irq;
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u32 ver_id;
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u8 rng_type;
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rngc = devm_kzalloc(&pdev->dev, sizeof(*rngc), GFP_KERNEL);
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if (!rngc)
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return -ENOMEM;
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rngc->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(rngc->base))
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return PTR_ERR(rngc->base);
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rngc->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(rngc->clk)) {
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dev_err(&pdev->dev, "Can not get rng_clk\n");
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return PTR_ERR(rngc->clk);
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}
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irq = platform_get_irq(pdev, 0);
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if (irq <= 0) {
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dev_err(&pdev->dev, "Couldn't get irq %d\n", irq);
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return irq;
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}
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ret = clk_prepare_enable(rngc->clk);
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if (ret)
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return ret;
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ver_id = readl(rngc->base + RNGC_VER_ID);
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rng_type = ver_id >> RNGC_TYPE_SHIFT;
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/*
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* This driver supports only RNGC and RNGB. (There's a different
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* driver for RNGA.)
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*/
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if (rng_type != RNGC_TYPE_RNGC && rng_type != RNGC_TYPE_RNGB) {
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ret = -ENODEV;
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goto err;
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}
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init_completion(&rngc->rng_op_done);
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rngc->rng.name = pdev->name;
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rngc->rng.init = imx_rngc_init;
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rngc->rng.read = imx_rngc_read;
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rngc->rng.cleanup = imx_rngc_cleanup;
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rngc->rng.quality = 19;
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rngc->dev = &pdev->dev;
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platform_set_drvdata(pdev, rngc);
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imx_rngc_irq_mask_clear(rngc);
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ret = devm_request_irq(&pdev->dev,
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irq, imx_rngc_irq, 0, pdev->name, (void *)rngc);
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if (ret) {
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dev_err(rngc->dev, "Can't get interrupt working.\n");
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return ret;
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}
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if (self_test) {
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ret = imx_rngc_self_test(rngc);
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if (ret) {
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dev_err(rngc->dev, "self test failed\n");
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goto err;
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}
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}
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ret = hwrng_register(&rngc->rng);
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if (ret) {
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dev_err(&pdev->dev, "hwrng registration failed\n");
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goto err;
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}
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dev_info(&pdev->dev,
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"Freescale RNG%c registered (HW revision %d.%02d)\n",
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rng_type == RNGC_TYPE_RNGB ? 'B' : 'C',
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(ver_id >> RNGC_VER_MAJ_SHIFT) & 0xff, ver_id & 0xff);
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return 0;
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err:
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clk_disable_unprepare(rngc->clk);
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return ret;
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}
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static int __exit imx_rngc_remove(struct platform_device *pdev)
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{
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struct imx_rngc *rngc = platform_get_drvdata(pdev);
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hwrng_unregister(&rngc->rng);
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clk_disable_unprepare(rngc->clk);
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return 0;
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}
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static int __maybe_unused imx_rngc_suspend(struct device *dev)
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{
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struct imx_rngc *rngc = dev_get_drvdata(dev);
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clk_disable_unprepare(rngc->clk);
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return 0;
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}
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static int __maybe_unused imx_rngc_resume(struct device *dev)
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{
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struct imx_rngc *rngc = dev_get_drvdata(dev);
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clk_prepare_enable(rngc->clk);
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return 0;
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}
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static SIMPLE_DEV_PM_OPS(imx_rngc_pm_ops, imx_rngc_suspend, imx_rngc_resume);
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static const struct of_device_id imx_rngc_dt_ids[] = {
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{ .compatible = "fsl,imx25-rngb", .data = NULL, },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, imx_rngc_dt_ids);
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static struct platform_driver imx_rngc_driver = {
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.driver = {
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.name = "imx_rngc",
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.pm = &imx_rngc_pm_ops,
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.of_match_table = imx_rngc_dt_ids,
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},
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.remove = __exit_p(imx_rngc_remove),
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};
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module_platform_driver_probe(imx_rngc_driver, imx_rngc_probe);
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MODULE_AUTHOR("Freescale Semiconductor, Inc.");
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MODULE_DESCRIPTION("H/W RNGC driver for i.MX");
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MODULE_LICENSE("GPL");
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