// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Support for the interrupt controllers found on Power Macintosh,
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* currently Apple's "Grand Central" interrupt controller in all
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* it's incarnations. OpenPIC support used on newer machines is
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* in a separate file
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*
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* Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
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* Copyright (C) 2005 Benjamin Herrenschmidt (benh@kernel.crashing.org)
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* IBM, Corp.
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*/
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#include <linux/stddef.h>
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/signal.h>
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include <linux/syscore_ops.h>
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#include <linux/adb.h>
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#include <linux/pmu.h>
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#include <asm/sections.h>
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#include <asm/io.h>
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#include <asm/smp.h>
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#include <asm/prom.h>
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#include <asm/pci-bridge.h>
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#include <asm/time.h>
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#include <asm/pmac_feature.h>
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#include <asm/mpic.h>
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#include <asm/xmon.h>
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#include "pmac.h"
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#ifdef CONFIG_PPC32
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struct pmac_irq_hw {
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unsigned int event;
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unsigned int enable;
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unsigned int ack;
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unsigned int level;
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};
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/* Workaround flags for 32bit powermac machines */
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unsigned int of_irq_workarounds;
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struct device_node *of_irq_dflt_pic;
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/* Default addresses */
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static volatile struct pmac_irq_hw __iomem *pmac_irq_hw[4];
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static int max_irqs;
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static int max_real_irqs;
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static DEFINE_RAW_SPINLOCK(pmac_pic_lock);
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/* The max irq number this driver deals with is 128; see max_irqs */
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static DECLARE_BITMAP(ppc_lost_interrupts, 128);
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static DECLARE_BITMAP(ppc_cached_irq_mask, 128);
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static int pmac_irq_cascade = -1;
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static struct irq_domain *pmac_pic_host;
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static void __pmac_retrigger(unsigned int irq_nr)
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{
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if (irq_nr >= max_real_irqs && pmac_irq_cascade > 0) {
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__set_bit(irq_nr, ppc_lost_interrupts);
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irq_nr = pmac_irq_cascade;
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mb();
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}
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if (!__test_and_set_bit(irq_nr, ppc_lost_interrupts)) {
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atomic_inc(&ppc_n_lost_interrupts);
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set_dec(1);
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}
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}
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static void pmac_mask_and_ack_irq(struct irq_data *d)
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{
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unsigned int src = irqd_to_hwirq(d);
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unsigned long bit = 1UL << (src & 0x1f);
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int i = src >> 5;
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unsigned long flags;
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raw_spin_lock_irqsave(&pmac_pic_lock, flags);
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__clear_bit(src, ppc_cached_irq_mask);
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if (__test_and_clear_bit(src, ppc_lost_interrupts))
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atomic_dec(&ppc_n_lost_interrupts);
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out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
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out_le32(&pmac_irq_hw[i]->ack, bit);
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do {
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/* make sure ack gets to controller before we enable
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interrupts */
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mb();
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} while((in_le32(&pmac_irq_hw[i]->enable) & bit)
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!= (ppc_cached_irq_mask[i] & bit));
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raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
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}
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static void pmac_ack_irq(struct irq_data *d)
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{
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unsigned int src = irqd_to_hwirq(d);
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unsigned long bit = 1UL << (src & 0x1f);
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int i = src >> 5;
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unsigned long flags;
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raw_spin_lock_irqsave(&pmac_pic_lock, flags);
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if (__test_and_clear_bit(src, ppc_lost_interrupts))
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atomic_dec(&ppc_n_lost_interrupts);
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out_le32(&pmac_irq_hw[i]->ack, bit);
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(void)in_le32(&pmac_irq_hw[i]->ack);
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raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
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}
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static void __pmac_set_irq_mask(unsigned int irq_nr, int nokicklost)
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{
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unsigned long bit = 1UL << (irq_nr & 0x1f);
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int i = irq_nr >> 5;
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if ((unsigned)irq_nr >= max_irqs)
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return;
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/* enable unmasked interrupts */
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out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
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do {
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/* make sure mask gets to controller before we
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return to user */
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mb();
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} while((in_le32(&pmac_irq_hw[i]->enable) & bit)
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!= (ppc_cached_irq_mask[i] & bit));
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/*
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* Unfortunately, setting the bit in the enable register
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* when the device interrupt is already on *doesn't* set
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* the bit in the flag register or request another interrupt.
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*/
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if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level))
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__pmac_retrigger(irq_nr);
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}
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/* When an irq gets requested for the first client, if it's an
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* edge interrupt, we clear any previous one on the controller
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*/
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static unsigned int pmac_startup_irq(struct irq_data *d)
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{
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unsigned long flags;
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unsigned int src = irqd_to_hwirq(d);
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unsigned long bit = 1UL << (src & 0x1f);
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int i = src >> 5;
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raw_spin_lock_irqsave(&pmac_pic_lock, flags);
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if (!irqd_is_level_type(d))
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out_le32(&pmac_irq_hw[i]->ack, bit);
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__set_bit(src, ppc_cached_irq_mask);
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__pmac_set_irq_mask(src, 0);
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raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
|
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return 0;
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}
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static void pmac_mask_irq(struct irq_data *d)
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{
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unsigned long flags;
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unsigned int src = irqd_to_hwirq(d);
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raw_spin_lock_irqsave(&pmac_pic_lock, flags);
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__clear_bit(src, ppc_cached_irq_mask);
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__pmac_set_irq_mask(src, 1);
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raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
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}
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static void pmac_unmask_irq(struct irq_data *d)
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{
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unsigned long flags;
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unsigned int src = irqd_to_hwirq(d);
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raw_spin_lock_irqsave(&pmac_pic_lock, flags);
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__set_bit(src, ppc_cached_irq_mask);
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__pmac_set_irq_mask(src, 0);
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raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
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}
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static int pmac_retrigger(struct irq_data *d)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&pmac_pic_lock, flags);
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__pmac_retrigger(irqd_to_hwirq(d));
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raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
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return 1;
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}
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static struct irq_chip pmac_pic = {
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.name = "PMAC-PIC",
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.irq_startup = pmac_startup_irq,
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.irq_mask = pmac_mask_irq,
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.irq_ack = pmac_ack_irq,
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.irq_mask_ack = pmac_mask_and_ack_irq,
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.irq_unmask = pmac_unmask_irq,
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.irq_retrigger = pmac_retrigger,
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};
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static irqreturn_t gatwick_action(int cpl, void *dev_id)
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{
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unsigned long flags;
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int irq, bits;
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int rc = IRQ_NONE;
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raw_spin_lock_irqsave(&pmac_pic_lock, flags);
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for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) {
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int i = irq >> 5;
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bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
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bits |= in_le32(&pmac_irq_hw[i]->level);
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bits &= ppc_cached_irq_mask[i];
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if (bits == 0)
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continue;
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irq += __ilog2(bits);
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raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
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generic_handle_irq(irq);
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raw_spin_lock_irqsave(&pmac_pic_lock, flags);
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rc = IRQ_HANDLED;
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}
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raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
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return rc;
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}
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static unsigned int pmac_pic_get_irq(void)
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{
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int irq;
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unsigned long bits = 0;
|
unsigned long flags;
|
|
#ifdef CONFIG_PPC_PMAC32_PSURGE
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/* IPI's are a hack on the powersurge -- Cort */
|
if (smp_processor_id() != 0) {
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return psurge_secondary_virq;
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}
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#endif /* CONFIG_PPC_PMAC32_PSURGE */
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raw_spin_lock_irqsave(&pmac_pic_lock, flags);
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for (irq = max_real_irqs; (irq -= 32) >= 0; ) {
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int i = irq >> 5;
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bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
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bits |= in_le32(&pmac_irq_hw[i]->level);
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bits &= ppc_cached_irq_mask[i];
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if (bits == 0)
|
continue;
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irq += __ilog2(bits);
|
break;
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}
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raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
|
if (unlikely(irq < 0))
|
return 0;
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return irq_linear_revmap(pmac_pic_host, irq);
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}
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static int pmac_pic_host_match(struct irq_domain *h, struct device_node *node,
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enum irq_domain_bus_token bus_token)
|
{
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/* We match all, we don't always have a node anyway */
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return 1;
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}
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static int pmac_pic_host_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
|
{
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if (hw >= max_irqs)
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return -EINVAL;
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|
/* Mark level interrupts, set delayed disable for edge ones and set
|
* handlers
|
*/
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irq_set_status_flags(virq, IRQ_LEVEL);
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irq_set_chip_and_handler(virq, &pmac_pic, handle_level_irq);
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return 0;
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}
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static const struct irq_domain_ops pmac_pic_host_ops = {
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.match = pmac_pic_host_match,
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.map = pmac_pic_host_map,
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.xlate = irq_domain_xlate_onecell,
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};
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static void __init pmac_pic_probe_oldstyle(void)
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{
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int i;
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struct device_node *master = NULL;
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struct device_node *slave = NULL;
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u8 __iomem *addr;
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struct resource r;
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/* Set our get_irq function */
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ppc_md.get_irq = pmac_pic_get_irq;
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/*
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* Find the interrupt controller type & node
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*/
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|
if ((master = of_find_node_by_name(NULL, "gc")) != NULL) {
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max_irqs = max_real_irqs = 32;
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} else if ((master = of_find_node_by_name(NULL, "ohare")) != NULL) {
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max_irqs = max_real_irqs = 32;
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/* We might have a second cascaded ohare */
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slave = of_find_node_by_name(NULL, "pci106b,7");
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if (slave)
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max_irqs = 64;
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} else if ((master = of_find_node_by_name(NULL, "mac-io")) != NULL) {
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max_irqs = max_real_irqs = 64;
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|
/* We might have a second cascaded heathrow */
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|
/* Compensate for of_node_put() in of_find_node_by_name() */
|
of_node_get(master);
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slave = of_find_node_by_name(master, "mac-io");
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/* Check ordering of master & slave */
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if (of_device_is_compatible(master, "gatwick")) {
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struct device_node *tmp;
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BUG_ON(slave == NULL);
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tmp = master;
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master = slave;
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slave = tmp;
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}
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|
/* We found a slave */
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if (slave)
|
max_irqs = 128;
|
}
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BUG_ON(master == NULL);
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/*
|
* Allocate an irq host
|
*/
|
pmac_pic_host = irq_domain_add_linear(master, max_irqs,
|
&pmac_pic_host_ops, NULL);
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BUG_ON(pmac_pic_host == NULL);
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irq_set_default_host(pmac_pic_host);
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/* Get addresses of first controller if we have a node for it */
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BUG_ON(of_address_to_resource(master, 0, &r));
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/* Map interrupts of primary controller */
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addr = (u8 __iomem *) ioremap(r.start, 0x40);
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i = 0;
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pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
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(addr + 0x20);
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if (max_real_irqs > 32)
|
pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
|
(addr + 0x10);
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of_node_put(master);
|
|
printk(KERN_INFO "irq: Found primary Apple PIC %pOF for %d irqs\n",
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master, max_real_irqs);
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|
/* Map interrupts of cascaded controller */
|
if (slave && !of_address_to_resource(slave, 0, &r)) {
|
addr = (u8 __iomem *)ioremap(r.start, 0x40);
|
pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
|
(addr + 0x20);
|
if (max_irqs > 64)
|
pmac_irq_hw[i++] =
|
(volatile struct pmac_irq_hw __iomem *)
|
(addr + 0x10);
|
pmac_irq_cascade = irq_of_parse_and_map(slave, 0);
|
|
printk(KERN_INFO "irq: Found slave Apple PIC %pOF for %d irqs"
|
" cascade: %d\n", slave,
|
max_irqs - max_real_irqs, pmac_irq_cascade);
|
}
|
of_node_put(slave);
|
|
/* Disable all interrupts in all controllers */
|
for (i = 0; i * 32 < max_irqs; ++i)
|
out_le32(&pmac_irq_hw[i]->enable, 0);
|
|
/* Hookup cascade irq */
|
if (slave && pmac_irq_cascade) {
|
if (request_irq(pmac_irq_cascade, gatwick_action,
|
IRQF_NO_THREAD, "cascade", NULL))
|
pr_err("Failed to register cascade interrupt\n");
|
}
|
|
printk(KERN_INFO "irq: System has %d possible interrupts\n", max_irqs);
|
#ifdef CONFIG_XMON
|
i = irq_create_mapping(NULL, 20);
|
if (request_irq(i, xmon_irq, IRQF_NO_THREAD, "NMI - XMON", NULL))
|
pr_err("Failed to register NMI-XMON interrupt\n");
|
#endif
|
}
|
|
int of_irq_parse_oldworld(struct device_node *device, int index,
|
struct of_phandle_args *out_irq)
|
{
|
const u32 *ints = NULL;
|
int intlen;
|
|
/*
|
* Old machines just have a list of interrupt numbers
|
* and no interrupt-controller nodes. We also have dodgy
|
* cases where the APPL,interrupts property is completely
|
* missing behind pci-pci bridges and we have to get it
|
* from the parent (the bridge itself, as apple just wired
|
* everything together on these)
|
*/
|
while (device) {
|
ints = of_get_property(device, "AAPL,interrupts", &intlen);
|
if (ints != NULL)
|
break;
|
device = device->parent;
|
if (!of_node_is_type(device, "pci"))
|
break;
|
}
|
if (ints == NULL)
|
return -EINVAL;
|
intlen /= sizeof(u32);
|
|
if (index >= intlen)
|
return -EINVAL;
|
|
out_irq->np = NULL;
|
out_irq->args[0] = ints[index];
|
out_irq->args_count = 1;
|
|
return 0;
|
}
|
#endif /* CONFIG_PPC32 */
|
|
static void __init pmac_pic_setup_mpic_nmi(struct mpic *mpic)
|
{
|
#if defined(CONFIG_XMON) && defined(CONFIG_PPC32)
|
struct device_node* pswitch;
|
int nmi_irq;
|
|
pswitch = of_find_node_by_name(NULL, "programmer-switch");
|
if (pswitch) {
|
nmi_irq = irq_of_parse_and_map(pswitch, 0);
|
if (nmi_irq) {
|
mpic_irq_set_priority(nmi_irq, 9);
|
if (request_irq(nmi_irq, xmon_irq, IRQF_NO_THREAD,
|
"NMI - XMON", NULL))
|
pr_err("Failed to register NMI-XMON interrupt\n");
|
}
|
of_node_put(pswitch);
|
}
|
#endif /* defined(CONFIG_XMON) && defined(CONFIG_PPC32) */
|
}
|
|
static struct mpic * __init pmac_setup_one_mpic(struct device_node *np,
|
int master)
|
{
|
const char *name = master ? " MPIC 1 " : " MPIC 2 ";
|
struct mpic *mpic;
|
unsigned int flags = master ? 0 : MPIC_SECONDARY;
|
|
pmac_call_feature(PMAC_FTR_ENABLE_MPIC, np, 0, 0);
|
|
if (of_get_property(np, "big-endian", NULL))
|
flags |= MPIC_BIG_ENDIAN;
|
|
/* Primary Big Endian means HT interrupts. This is quite dodgy
|
* but works until I find a better way
|
*/
|
if (master && (flags & MPIC_BIG_ENDIAN))
|
flags |= MPIC_U3_HT_IRQS;
|
|
mpic = mpic_alloc(np, 0, flags, 0, 0, name);
|
if (mpic == NULL)
|
return NULL;
|
|
mpic_init(mpic);
|
|
return mpic;
|
}
|
|
static int __init pmac_pic_probe_mpic(void)
|
{
|
struct mpic *mpic1, *mpic2;
|
struct device_node *np, *master = NULL, *slave = NULL;
|
|
/* We can have up to 2 MPICs cascaded */
|
for_each_node_by_type(np, "open-pic") {
|
if (master == NULL &&
|
of_get_property(np, "interrupts", NULL) == NULL)
|
master = of_node_get(np);
|
else if (slave == NULL)
|
slave = of_node_get(np);
|
if (master && slave) {
|
of_node_put(np);
|
break;
|
}
|
}
|
|
/* Check for bogus setups */
|
if (master == NULL && slave != NULL) {
|
master = slave;
|
slave = NULL;
|
}
|
|
/* Not found, default to good old pmac pic */
|
if (master == NULL)
|
return -ENODEV;
|
|
/* Set master handler */
|
ppc_md.get_irq = mpic_get_irq;
|
|
/* Setup master */
|
mpic1 = pmac_setup_one_mpic(master, 1);
|
BUG_ON(mpic1 == NULL);
|
|
/* Install NMI if any */
|
pmac_pic_setup_mpic_nmi(mpic1);
|
|
of_node_put(master);
|
|
/* Set up a cascaded controller, if present */
|
if (slave) {
|
mpic2 = pmac_setup_one_mpic(slave, 0);
|
if (mpic2 == NULL)
|
printk(KERN_ERR "Failed to setup slave MPIC\n");
|
of_node_put(slave);
|
}
|
|
return 0;
|
}
|
|
|
void __init pmac_pic_init(void)
|
{
|
/* We configure the OF parsing based on our oldworld vs. newworld
|
* platform type and whether we were booted by BootX.
|
*/
|
#ifdef CONFIG_PPC32
|
if (!pmac_newworld)
|
of_irq_workarounds |= OF_IMAP_OLDWORLD_MAC;
|
if (of_get_property(of_chosen, "linux,bootx", NULL) != NULL)
|
of_irq_workarounds |= OF_IMAP_NO_PHANDLE;
|
|
/* If we don't have phandles on a newworld, then try to locate a
|
* default interrupt controller (happens when booting with BootX).
|
* We do a first match here, hopefully, that only ever happens on
|
* machines with one controller.
|
*/
|
if (pmac_newworld && (of_irq_workarounds & OF_IMAP_NO_PHANDLE)) {
|
struct device_node *np;
|
|
for_each_node_with_property(np, "interrupt-controller") {
|
/* Skip /chosen/interrupt-controller */
|
if (of_node_name_eq(np, "chosen"))
|
continue;
|
/* It seems like at least one person wants
|
* to use BootX on a machine with an AppleKiwi
|
* controller which happens to pretend to be an
|
* interrupt controller too. */
|
if (of_node_name_eq(np, "AppleKiwi"))
|
continue;
|
/* I think we found one ! */
|
of_irq_dflt_pic = np;
|
break;
|
}
|
}
|
#endif /* CONFIG_PPC32 */
|
|
/* We first try to detect Apple's new Core99 chipset, since mac-io
|
* is quite different on those machines and contains an IBM MPIC2.
|
*/
|
if (pmac_pic_probe_mpic() == 0)
|
return;
|
|
#ifdef CONFIG_PPC32
|
pmac_pic_probe_oldstyle();
|
#endif
|
}
|
|
#if defined(CONFIG_PM) && defined(CONFIG_PPC32)
|
/*
|
* These procedures are used in implementing sleep on the powerbooks.
|
* sleep_save_intrs() saves the states of all interrupt enables
|
* and disables all interrupts except for the nominated one.
|
* sleep_restore_intrs() restores the states of all interrupt enables.
|
*/
|
unsigned long sleep_save_mask[2];
|
|
/* This used to be passed by the PMU driver but that link got
|
* broken with the new driver model. We use this tweak for now...
|
* We really want to do things differently though...
|
*/
|
static int pmacpic_find_viaint(void)
|
{
|
int viaint = -1;
|
|
#ifdef CONFIG_ADB_PMU
|
struct device_node *np;
|
|
if (pmu_get_model() != PMU_OHARE_BASED)
|
goto not_found;
|
np = of_find_node_by_name(NULL, "via-pmu");
|
if (np == NULL)
|
goto not_found;
|
viaint = irq_of_parse_and_map(np, 0);
|
of_node_put(np);
|
|
not_found:
|
#endif /* CONFIG_ADB_PMU */
|
return viaint;
|
}
|
|
static int pmacpic_suspend(void)
|
{
|
int viaint = pmacpic_find_viaint();
|
|
sleep_save_mask[0] = ppc_cached_irq_mask[0];
|
sleep_save_mask[1] = ppc_cached_irq_mask[1];
|
ppc_cached_irq_mask[0] = 0;
|
ppc_cached_irq_mask[1] = 0;
|
if (viaint > 0)
|
set_bit(viaint, ppc_cached_irq_mask);
|
out_le32(&pmac_irq_hw[0]->enable, ppc_cached_irq_mask[0]);
|
if (max_real_irqs > 32)
|
out_le32(&pmac_irq_hw[1]->enable, ppc_cached_irq_mask[1]);
|
(void)in_le32(&pmac_irq_hw[0]->event);
|
/* make sure mask gets to controller before we return to caller */
|
mb();
|
(void)in_le32(&pmac_irq_hw[0]->enable);
|
|
return 0;
|
}
|
|
static void pmacpic_resume(void)
|
{
|
int i;
|
|
out_le32(&pmac_irq_hw[0]->enable, 0);
|
if (max_real_irqs > 32)
|
out_le32(&pmac_irq_hw[1]->enable, 0);
|
mb();
|
for (i = 0; i < max_real_irqs; ++i)
|
if (test_bit(i, sleep_save_mask))
|
pmac_unmask_irq(irq_get_irq_data(i));
|
}
|
|
static struct syscore_ops pmacpic_syscore_ops = {
|
.suspend = pmacpic_suspend,
|
.resume = pmacpic_resume,
|
};
|
|
static int __init init_pmacpic_syscore(void)
|
{
|
if (pmac_irq_hw[0])
|
register_syscore_ops(&pmacpic_syscore_ops);
|
return 0;
|
}
|
|
machine_subsys_initcall(powermac, init_pmacpic_syscore);
|
|
#endif /* CONFIG_PM && CONFIG_PPC32 */
|
