// SPDX-License-Identifier: GPL-2.0-only
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/*
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*
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* Copyright (C) 2010 John Crispin <john@phrozen.org>
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/mm.h>
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#include <linux/vmalloc.h>
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#include <linux/clk.h>
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#include <linux/of_platform.h>
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#include <linux/of_gpio.h>
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#include <linux/of_irq.h>
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#include <linux/of_pci.h>
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#include <asm/addrspace.h>
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#include <lantiq_soc.h>
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#include <lantiq_irq.h>
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#include "pci-lantiq.h"
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#define PCI_CR_FCI_ADDR_MAP0 0x00C0
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#define PCI_CR_FCI_ADDR_MAP1 0x00C4
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#define PCI_CR_FCI_ADDR_MAP2 0x00C8
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#define PCI_CR_FCI_ADDR_MAP3 0x00CC
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#define PCI_CR_FCI_ADDR_MAP4 0x00D0
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#define PCI_CR_FCI_ADDR_MAP5 0x00D4
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#define PCI_CR_FCI_ADDR_MAP6 0x00D8
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#define PCI_CR_FCI_ADDR_MAP7 0x00DC
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#define PCI_CR_CLK_CTRL 0x0000
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#define PCI_CR_PCI_MOD 0x0030
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#define PCI_CR_PC_ARB 0x0080
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#define PCI_CR_FCI_ADDR_MAP11hg 0x00E4
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#define PCI_CR_BAR11MASK 0x0044
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#define PCI_CR_BAR12MASK 0x0048
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#define PCI_CR_BAR13MASK 0x004C
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#define PCI_CS_BASE_ADDR1 0x0010
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#define PCI_CR_PCI_ADDR_MAP11 0x0064
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#define PCI_CR_FCI_BURST_LENGTH 0x00E8
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#define PCI_CR_PCI_EOI 0x002C
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#define PCI_CS_STS_CMD 0x0004
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#define PCI_MASTER0_REQ_MASK_2BITS 8
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#define PCI_MASTER1_REQ_MASK_2BITS 10
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#define PCI_MASTER2_REQ_MASK_2BITS 12
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#define INTERNAL_ARB_ENABLE_BIT 0
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#define LTQ_CGU_IFCCR 0x0018
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#define LTQ_CGU_PCICR 0x0034
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#define ltq_pci_w32(x, y) ltq_w32((x), ltq_pci_membase + (y))
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#define ltq_pci_r32(x) ltq_r32(ltq_pci_membase + (x))
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#define ltq_pci_cfg_w32(x, y) ltq_w32((x), ltq_pci_mapped_cfg + (y))
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#define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_mapped_cfg + (x))
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__iomem void *ltq_pci_mapped_cfg;
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static __iomem void *ltq_pci_membase;
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static int reset_gpio;
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static struct clk *clk_pci, *clk_external;
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static struct resource pci_io_resource;
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static struct resource pci_mem_resource;
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static struct pci_ops pci_ops = {
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.read = ltq_pci_read_config_dword,
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.write = ltq_pci_write_config_dword
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};
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static struct pci_controller pci_controller = {
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.pci_ops = &pci_ops,
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.mem_resource = &pci_mem_resource,
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.mem_offset = 0x00000000UL,
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.io_resource = &pci_io_resource,
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.io_offset = 0x00000000UL,
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};
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static inline u32 ltq_calc_bar11mask(void)
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{
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u32 mem, bar11mask;
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/* BAR11MASK value depends on available memory on system. */
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mem = get_num_physpages() * PAGE_SIZE;
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bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) - 1)) - 1)) | 8;
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return bar11mask;
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}
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static int ltq_pci_startup(struct platform_device *pdev)
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{
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struct device_node *node = pdev->dev.of_node;
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const __be32 *req_mask, *bus_clk;
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u32 temp_buffer;
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/* get our clocks */
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clk_pci = clk_get(&pdev->dev, NULL);
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if (IS_ERR(clk_pci)) {
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dev_err(&pdev->dev, "failed to get pci clock\n");
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return PTR_ERR(clk_pci);
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}
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clk_external = clk_get(&pdev->dev, "external");
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if (IS_ERR(clk_external)) {
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clk_put(clk_pci);
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dev_err(&pdev->dev, "failed to get external pci clock\n");
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return PTR_ERR(clk_external);
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}
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/* read the bus speed that we want */
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bus_clk = of_get_property(node, "lantiq,bus-clock", NULL);
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if (bus_clk)
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clk_set_rate(clk_pci, *bus_clk);
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/* and enable the clocks */
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clk_enable(clk_pci);
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if (of_find_property(node, "lantiq,external-clock", NULL))
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clk_enable(clk_external);
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else
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clk_disable(clk_external);
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/* setup reset gpio used by pci */
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reset_gpio = of_get_named_gpio(node, "gpio-reset", 0);
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if (gpio_is_valid(reset_gpio)) {
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int ret = devm_gpio_request(&pdev->dev,
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reset_gpio, "pci-reset");
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if (ret) {
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dev_err(&pdev->dev,
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"failed to request gpio %d\n", reset_gpio);
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return ret;
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}
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gpio_direction_output(reset_gpio, 1);
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}
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/* enable auto-switching between PCI and EBU */
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ltq_pci_w32(0xa, PCI_CR_CLK_CTRL);
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/* busy, i.e. configuration is not done, PCI access has to be retried */
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ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD);
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wmb();
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/* BUS Master/IO/MEM access */
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ltq_pci_cfg_w32(ltq_pci_cfg_r32(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD);
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/* enable external 2 PCI masters */
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temp_buffer = ltq_pci_r32(PCI_CR_PC_ARB);
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/* setup the request mask */
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req_mask = of_get_property(node, "req-mask", NULL);
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if (req_mask)
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temp_buffer &= ~((*req_mask & 0xf) << 16);
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else
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temp_buffer &= ~0xf0000;
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/* enable internal arbiter */
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temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT);
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/* enable internal PCI master reqest */
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temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS));
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/* enable EBU request */
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temp_buffer &= (~(3 << PCI_MASTER1_REQ_MASK_2BITS));
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/* enable all external masters request */
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temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS));
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ltq_pci_w32(temp_buffer, PCI_CR_PC_ARB);
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wmb();
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/* setup BAR memory regions */
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ltq_pci_w32(0x18000000, PCI_CR_FCI_ADDR_MAP0);
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ltq_pci_w32(0x18400000, PCI_CR_FCI_ADDR_MAP1);
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ltq_pci_w32(0x18800000, PCI_CR_FCI_ADDR_MAP2);
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ltq_pci_w32(0x18c00000, PCI_CR_FCI_ADDR_MAP3);
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ltq_pci_w32(0x19000000, PCI_CR_FCI_ADDR_MAP4);
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ltq_pci_w32(0x19400000, PCI_CR_FCI_ADDR_MAP5);
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ltq_pci_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6);
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ltq_pci_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7);
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ltq_pci_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg);
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ltq_pci_w32(ltq_calc_bar11mask(), PCI_CR_BAR11MASK);
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ltq_pci_w32(0, PCI_CR_PCI_ADDR_MAP11);
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ltq_pci_w32(0, PCI_CS_BASE_ADDR1);
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/* both TX and RX endian swap are enabled */
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ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI);
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wmb();
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ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR12MASK) | 0x80000000,
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PCI_CR_BAR12MASK);
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ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR13MASK) | 0x80000000,
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PCI_CR_BAR13MASK);
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/*use 8 dw burst length */
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ltq_pci_w32(0x303, PCI_CR_FCI_BURST_LENGTH);
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ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
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wmb();
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/* setup irq line */
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ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_CON) | 0xc, LTQ_EBU_PCC_CON);
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ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_IEN) | 0x10, LTQ_EBU_PCC_IEN);
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/* toggle reset pin */
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if (gpio_is_valid(reset_gpio)) {
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__gpio_set_value(reset_gpio, 0);
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wmb();
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mdelay(1);
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__gpio_set_value(reset_gpio, 1);
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}
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return 0;
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}
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static int ltq_pci_probe(struct platform_device *pdev)
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{
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struct resource *res_cfg, *res_bridge;
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pci_clear_flags(PCI_PROBE_ONLY);
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res_bridge = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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ltq_pci_membase = devm_ioremap_resource(&pdev->dev, res_bridge);
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if (IS_ERR(ltq_pci_membase))
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return PTR_ERR(ltq_pci_membase);
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res_cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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ltq_pci_mapped_cfg = devm_ioremap_resource(&pdev->dev, res_cfg);
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if (IS_ERR(ltq_pci_mapped_cfg))
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return PTR_ERR(ltq_pci_mapped_cfg);
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ltq_pci_startup(pdev);
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pci_load_of_ranges(&pci_controller, pdev->dev.of_node);
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register_pci_controller(&pci_controller);
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return 0;
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}
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static const struct of_device_id ltq_pci_match[] = {
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{ .compatible = "lantiq,pci-xway" },
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{},
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};
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static struct platform_driver ltq_pci_driver = {
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.probe = ltq_pci_probe,
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.driver = {
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.name = "pci-xway",
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.of_match_table = ltq_pci_match,
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},
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};
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int __init pcibios_init(void)
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{
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int ret = platform_driver_register(<q_pci_driver);
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if (ret)
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pr_info("pci-xway: Error registering platform driver!");
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return ret;
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}
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arch_initcall(pcibios_init);
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