.. SPDX-License-Identifier: GPL-2.0
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==================================================
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ARM Virtual Generic Interrupt Controller v2 (VGIC)
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==================================================
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Device types supported:
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- KVM_DEV_TYPE_ARM_VGIC_V2 ARM Generic Interrupt Controller v2.0
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Only one VGIC instance may be instantiated through either this API or the
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legacy KVM_CREATE_IRQCHIP API. The created VGIC will act as the VM interrupt
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controller, requiring emulated user-space devices to inject interrupts to the
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VGIC instead of directly to CPUs.
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GICv3 implementations with hardware compatibility support allow creating a
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guest GICv2 through this interface. For information on creating a guest GICv3
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device and guest ITS devices, see arm-vgic-v3.txt. It is not possible to
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create both a GICv3 and GICv2 device on the same VM.
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Groups:
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KVM_DEV_ARM_VGIC_GRP_ADDR
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Attributes:
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KVM_VGIC_V2_ADDR_TYPE_DIST (rw, 64-bit)
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Base address in the guest physical address space of the GIC distributor
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register mappings. Only valid for KVM_DEV_TYPE_ARM_VGIC_V2.
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This address needs to be 4K aligned and the region covers 4 KByte.
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KVM_VGIC_V2_ADDR_TYPE_CPU (rw, 64-bit)
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Base address in the guest physical address space of the GIC virtual cpu
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interface register mappings. Only valid for KVM_DEV_TYPE_ARM_VGIC_V2.
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This address needs to be 4K aligned and the region covers 4 KByte.
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Errors:
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======= =============================================================
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-E2BIG Address outside of addressable IPA range
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-EINVAL Incorrectly aligned address
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-EEXIST Address already configured
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-ENXIO The group or attribute is unknown/unsupported for this device
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or hardware support is missing.
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-EFAULT Invalid user pointer for attr->addr.
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======= =============================================================
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KVM_DEV_ARM_VGIC_GRP_DIST_REGS
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Attributes:
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The attr field of kvm_device_attr encodes two values::
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bits: | 63 .... 40 | 39 .. 32 | 31 .... 0 |
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values: | reserved | vcpu_index | offset |
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All distributor regs are (rw, 32-bit)
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The offset is relative to the "Distributor base address" as defined in the
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GICv2 specs. Getting or setting such a register has the same effect as
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reading or writing the register on the actual hardware from the cpu whose
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index is specified with the vcpu_index field. Note that most distributor
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fields are not banked, but return the same value regardless of the
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vcpu_index used to access the register.
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GICD_IIDR.Revision is updated when the KVM implementation of an emulated
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GICv2 is changed in a way directly observable by the guest or userspace.
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Userspace should read GICD_IIDR from KVM and write back the read value to
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confirm its expected behavior is aligned with the KVM implementation.
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Userspace should set GICD_IIDR before setting any other registers (both
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KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_CPU_REGS) to ensure
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the expected behavior. Unless GICD_IIDR has been set from userspace, writes
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to the interrupt group registers (GICD_IGROUPR) are ignored.
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Errors:
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======= =====================================================
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-ENXIO Getting or setting this register is not yet supported
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-EBUSY One or more VCPUs are running
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-EINVAL Invalid vcpu_index supplied
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======= =====================================================
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KVM_DEV_ARM_VGIC_GRP_CPU_REGS
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Attributes:
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The attr field of kvm_device_attr encodes two values::
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bits: | 63 .... 40 | 39 .. 32 | 31 .... 0 |
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values: | reserved | vcpu_index | offset |
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All CPU interface regs are (rw, 32-bit)
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The offset specifies the offset from the "CPU interface base address" as
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defined in the GICv2 specs. Getting or setting such a register has the
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same effect as reading or writing the register on the actual hardware.
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The Active Priorities Registers APRn are implementation defined, so we set a
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fixed format for our implementation that fits with the model of a "GICv2
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implementation without the security extensions" which we present to the
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guest. This interface always exposes four register APR[0-3] describing the
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maximum possible 128 preemption levels. The semantics of the register
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indicate if any interrupts in a given preemption level are in the active
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state by setting the corresponding bit.
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Thus, preemption level X has one or more active interrupts if and only if:
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APRn[X mod 32] == 0b1, where n = X / 32
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Bits for undefined preemption levels are RAZ/WI.
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Note that this differs from a CPU's view of the APRs on hardware in which
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a GIC without the security extensions expose group 0 and group 1 active
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priorities in separate register groups, whereas we show a combined view
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similar to GICv2's GICH_APR.
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For historical reasons and to provide ABI compatibility with userspace we
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export the GICC_PMR register in the format of the GICH_VMCR.VMPriMask
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field in the lower 5 bits of a word, meaning that userspace must always
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use the lower 5 bits to communicate with the KVM device and must shift the
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value left by 3 places to obtain the actual priority mask level.
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Errors:
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======= =====================================================
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-ENXIO Getting or setting this register is not yet supported
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-EBUSY One or more VCPUs are running
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-EINVAL Invalid vcpu_index supplied
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======= =====================================================
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KVM_DEV_ARM_VGIC_GRP_NR_IRQS
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Attributes:
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A value describing the number of interrupts (SGI, PPI and SPI) for
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this GIC instance, ranging from 64 to 1024, in increments of 32.
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Errors:
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======= =============================================================
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-EINVAL Value set is out of the expected range
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-EBUSY Value has already be set, or GIC has already been initialized
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with default values.
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======= =============================================================
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KVM_DEV_ARM_VGIC_GRP_CTRL
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Attributes:
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KVM_DEV_ARM_VGIC_CTRL_INIT
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request the initialization of the VGIC or ITS, no additional parameter
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in kvm_device_attr.addr.
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Errors:
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======= =========================================================
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-ENXIO VGIC not properly configured as required prior to calling
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this attribute
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-ENODEV no online VCPU
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-ENOMEM memory shortage when allocating vgic internal data
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======= =========================================================
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