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<title>Debugging with GDB: SPU</title>
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<a name="SPU"></a>
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<div class="header">
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<p>
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Next: <a href="PowerPC.html#PowerPC" accesskey="n" rel="next">PowerPC</a>, Previous: <a href="HPPA.html#HPPA" accesskey="p" rel="prev">HPPA</a>, Up: <a href="Architectures.html#Architectures" accesskey="u" rel="up">Architectures</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Concept-Index.html#Concept-Index" title="Index" rel="index">Index</a>]</p>
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<hr>
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<a name="Cell-Broadband-Engine-SPU-architecture"></a>
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<h4 class="subsection">21.4.6 Cell Broadband Engine SPU architecture</h4>
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<a name="index-Cell-Broadband-Engine"></a>
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<a name="index-SPU"></a>
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<p>When <small>GDB</small> is debugging the Cell Broadband Engine SPU architecture,
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it provides the following special commands:
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</p>
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<dl compact="compact">
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<dt><code>info spu event</code></dt>
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<dd><a name="index-info-spu"></a>
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<p>Display SPU event facility status. Shows current event mask
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and pending event status.
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</p>
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</dd>
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<dt><code>info spu signal</code></dt>
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<dd><p>Display SPU signal notification facility status. Shows pending
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signal-control word and signal notification mode of both signal
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notification channels.
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</p>
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</dd>
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<dt><code>info spu mailbox</code></dt>
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<dd><p>Display SPU mailbox facility status. Shows all pending entries,
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in order of processing, in each of the SPU Write Outbound,
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SPU Write Outbound Interrupt, and SPU Read Inbound mailboxes.
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</p>
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</dd>
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<dt><code>info spu dma</code></dt>
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<dd><p>Display MFC DMA status. Shows all pending commands in the MFC
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DMA queue. For each entry, opcode, tag, class IDs, effective
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and local store addresses and transfer size are shown.
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</p>
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</dd>
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<dt><code>info spu proxydma</code></dt>
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<dd><p>Display MFC Proxy-DMA status. Shows all pending commands in the MFC
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Proxy-DMA queue. For each entry, opcode, tag, class IDs, effective
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and local store addresses and transfer size are shown.
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</p>
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</dd>
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</dl>
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<p>When <small>GDB</small> is debugging a combined PowerPC/SPU application
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on the Cell Broadband Engine, it provides in addition the following
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special commands:
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</p>
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<dl compact="compact">
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<dt><code>set spu stop-on-load <var>arg</var></code></dt>
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<dd><a name="index-set-spu"></a>
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<p>Set whether to stop for new SPE threads. When set to <code>on</code>, <small>GDB</small>
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will give control to the user when a new SPE thread enters its <code>main</code>
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function. The default is <code>off</code>.
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</p>
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</dd>
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<dt><code>show spu stop-on-load</code></dt>
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<dd><a name="index-show-spu"></a>
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<p>Show whether to stop for new SPE threads.
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</p>
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</dd>
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<dt><code>set spu auto-flush-cache <var>arg</var></code></dt>
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<dd><p>Set whether to automatically flush the software-managed cache. When set to
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<code>on</code>, <small>GDB</small> will automatically cause the SPE software-managed
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cache to be flushed whenever SPE execution stops. This provides a consistent
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view of PowerPC memory that is accessed via the cache. If an application
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does not use the software-managed cache, this option has no effect.
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</p>
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</dd>
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<dt><code>show spu auto-flush-cache</code></dt>
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<dd><p>Show whether to automatically flush the software-managed cache.
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</p>
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</dd>
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</dl>
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<hr>
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<p>
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Next: <a href="PowerPC.html#PowerPC" accesskey="n" rel="next">PowerPC</a>, Previous: <a href="HPPA.html#HPPA" accesskey="p" rel="prev">HPPA</a>, Up: <a href="Architectures.html#Architectures" accesskey="u" rel="up">Architectures</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Concept-Index.html#Concept-Index" title="Index" rel="index">Index</a>]</p>
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