/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2020 NVIDIA CORPORATION. All rights reserved.
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*/
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#ifndef __TEGRA_CSI_H__
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#define __TEGRA_CSI_H__
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#include <media/media-entity.h>
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#include <media/v4l2-async.h>
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#include <media/v4l2-subdev.h>
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/*
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* Each CSI brick supports max of 4 lanes that can be used as either
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* one x4 port using both CILA and CILB partitions of a CSI brick or can
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* be used as two x2 ports with one x2 from CILA and the other x2 from
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* CILB.
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*/
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#define CSI_PORTS_PER_BRICK 2
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/* each CSI channel can have one sink and one source pads */
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#define TEGRA_CSI_PADS_NUM 2
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enum tegra_csi_cil_port {
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PORT_A = 0,
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PORT_B,
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};
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enum tegra_csi_block {
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CSI_CIL_AB = 0,
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CSI_CIL_CD,
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CSI_CIL_EF,
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};
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struct tegra_csi;
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/**
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* struct tegra_csi_channel - Tegra CSI channel
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*
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* @list: list head for this entry
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* @subdev: V4L2 subdevice associated with this channel
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* @pads: media pads for the subdevice entity
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* @numpads: number of pads.
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* @csi: Tegra CSI device structure
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* @of_node: csi device tree node
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* @numlanes: number of lanes used per port/channel
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* @csi_port_num: CSI channel port number
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* @pg_mode: test pattern generator mode for channel
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* @format: active format of the channel
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* @framerate: active framerate for TPG
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* @h_blank: horizontal blanking for TPG active format
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* @v_blank: vertical blanking for TPG active format
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* @mipi: mipi device for corresponding csi channel pads, or NULL if not applicable (TPG, error)
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* @pixel_rate: active pixel rate from the sensor on this channel
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*/
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struct tegra_csi_channel {
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struct list_head list;
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struct v4l2_subdev subdev;
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struct media_pad pads[TEGRA_CSI_PADS_NUM];
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unsigned int numpads;
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struct tegra_csi *csi;
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struct device_node *of_node;
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unsigned int numlanes;
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u8 csi_port_num;
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u8 pg_mode;
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struct v4l2_mbus_framefmt format;
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unsigned int framerate;
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unsigned int h_blank;
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unsigned int v_blank;
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struct tegra_mipi_device *mipi;
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unsigned int pixel_rate;
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};
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/**
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* struct tpg_framerate - Tegra CSI TPG framerate configuration
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*
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* @frmsize: frame resolution
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* @code: media bus format code
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* @h_blank: horizontal blanking used for TPG
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* @v_blank: vertical blanking interval used for TPG
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* @framerate: framerate achieved with the corresponding blanking intervals,
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* format and resolution.
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*/
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struct tpg_framerate {
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struct v4l2_frmsize_discrete frmsize;
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u32 code;
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unsigned int h_blank;
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unsigned int v_blank;
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unsigned int framerate;
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};
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/**
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* struct tegra_csi_ops - Tegra CSI operations
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*
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* @csi_start_streaming: programs csi hardware to enable streaming.
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* @csi_stop_streaming: programs csi hardware to disable streaming.
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* @csi_err_recover: csi hardware block recovery in case of any capture errors
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* due to missing source stream or due to improper csi input from
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* the external source.
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*/
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struct tegra_csi_ops {
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int (*csi_start_streaming)(struct tegra_csi_channel *csi_chan);
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void (*csi_stop_streaming)(struct tegra_csi_channel *csi_chan);
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void (*csi_err_recover)(struct tegra_csi_channel *csi_chan);
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};
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/**
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* struct tegra_csi_soc - NVIDIA Tegra CSI SoC structure
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*
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* @ops: csi hardware operations
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* @csi_max_channels: supported max streaming channels
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* @clk_names: csi and cil clock names
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* @num_clks: total clocks count
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* @tpg_frmrate_table: csi tpg frame rate table with blanking intervals
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* @tpg_frmrate_table_size: size of frame rate table
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*/
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struct tegra_csi_soc {
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const struct tegra_csi_ops *ops;
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unsigned int csi_max_channels;
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const char * const *clk_names;
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unsigned int num_clks;
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const struct tpg_framerate *tpg_frmrate_table;
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unsigned int tpg_frmrate_table_size;
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};
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/**
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* struct tegra_csi - NVIDIA Tegra CSI device structure
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*
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* @dev: device struct
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* @client: host1x_client struct
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* @iomem: register base
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* @clks: clock for CSI and CIL
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* @soc: pointer to SoC data structure
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* @ops: csi operations
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* @channels: list head for CSI channels
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*/
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struct tegra_csi {
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struct device *dev;
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struct host1x_client client;
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void __iomem *iomem;
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struct clk_bulk_data *clks;
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const struct tegra_csi_soc *soc;
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const struct tegra_csi_ops *ops;
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struct list_head csi_chans;
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};
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#if defined(CONFIG_ARCH_TEGRA_210_SOC)
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extern const struct tegra_csi_soc tegra210_csi_soc;
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#endif
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void tegra_csi_error_recover(struct v4l2_subdev *subdev);
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void tegra_csi_calc_settle_time(struct tegra_csi_channel *csi_chan,
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u8 *clk_settle_time,
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u8 *ths_settle_time);
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#endif
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