// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* maxim-nca9539.c -- I2C register interface access for nca9539 chip
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*
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* Copyright (c) 2023-2028 Rockchip Electronics Co. Ltd.
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*
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* Author: luowei <lw@rock-chips.com>
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*/
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#include "../core.h"
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#define REG_NCA9539_INPUT_PORT0 0x00 //Read only default 1111 1111
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#define REG_NCA9539_INPUT_PORT1 0x01 //Read only default 1111 1111
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#define REG_NCA9539_OUT_LEVEL_PORT0 0x02 //Read/write default 1111 1111
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#define REG_NCA9539_OUT_LEVEL_PORT1 0x03 //Read/write default 1111 1111
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#define REG_NCA9539_INVER_PORT0 0x04 //Read/write default 0000 0000
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#define REG_NCA9539_INVER_PORT1 0x05 //Read/write default 0000 0000
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#define REG_NCA9539_DIR_PORT0 0x06 //Read/write byte 1111 1111
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#define REG_NCA9539_DIR_PORT1 0x07 //Read/write byte 1111 1111
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static bool nca9539_volatile_reg(struct device *dev, unsigned int reg)
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{
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return true;
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}
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static struct regmap_config nca9539_regmap_config = {
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.name = "nca9539",
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.reg_bits = 8,
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.val_bits = 8,
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.max_register = 0x0007,
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.volatile_reg = nca9539_volatile_reg,
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.cache_type = REGCACHE_RBTREE,
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};
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static int NCA9539_GPIO0_pins[] = {0};
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static int NCA9539_GPIO1_pins[] = {1};
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static int NCA9539_GPIO2_pins[] = {2};
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static int NCA9539_GPIO3_pins[] = {3};
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static int NCA9539_GPIO4_pins[] = {4};
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static int NCA9539_GPIO5_pins[] = {5};
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static int NCA9539_GPIO6_pins[] = {6};
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static int NCA9539_GPIO7_pins[] = {7};
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static int NCA9539_GPIO8_pins[] = {8};
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static int NCA9539_GPIO9_pins[] = {9};
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static int NCA9539_GPIO10_pins[] = {10};
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static int NCA9539_GPIO11_pins[] = {11};
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static int NCA9539_GPIO12_pins[] = {12};
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static int NCA9539_GPIO13_pins[] = {13};
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static int NCA9539_GPIO14_pins[] = {14};
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static int NCA9539_GPIO15_pins[] = {15};
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#define GROUP_DESC(nm) \
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{ \
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.name = #nm, \
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.pins = nm ## _pins, \
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.num_pins = ARRAY_SIZE(nm ## _pins), \
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}
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static const char *serdes_gpio_groups[] = {
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"NCA9539_GPIO0", "NCA9539_GPIO1", "NCA9539_GPIO2", "NCA9539_GPIO3",
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"NCA9539_GPIO4", "NCA9539_GPIO5", "NCA9539_GPIO6", "NCA9539_GPIO7",
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"NCA9539_GPIO8", "NCA9539_GPIO9", "NCA9539_GPIO10", "NCA9539_GPIO11",
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"NCA9539_GPIO12", "NCA9539_GPIO13", "NCA9539_GPIO14", "NCA9539_GPIO15",
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};
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/*des -> ser -> soc*/
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#define FUNCTION_DESC_GPIO_INPUT(id) \
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{ \
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.name = "GPIO"#id"_INPUT", \
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.group_names = serdes_gpio_groups, \
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.num_group_names = ARRAY_SIZE(serdes_gpio_groups), \
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} \
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/*soc -> ser -> des*/
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#define FUNCTION_DESC_GPIO_OUTPUT(id) \
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{ \
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.name = "GPIO"#id"_OUTPUT", \
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.group_names = serdes_gpio_groups, \
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.num_group_names = ARRAY_SIZE(serdes_gpio_groups), \
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} \
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static struct pinctrl_pin_desc nca9539_pins_desc[] = {
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PINCTRL_PIN(NOVO_NCA9539_GPIO0, "NCA9539_GPIO0"),
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PINCTRL_PIN(NOVO_NCA9539_GPIO1, "NCA9539_GPIO1"),
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PINCTRL_PIN(NOVO_NCA9539_GPIO2, "NCA9539_GPIO2"),
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PINCTRL_PIN(NOVO_NCA9539_GPIO3, "NCA9539_GPIO3"),
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PINCTRL_PIN(NOVO_NCA9539_GPIO4, "NCA9539_GPIO4"),
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PINCTRL_PIN(NOVO_NCA9539_GPIO5, "NCA9539_GPIO5"),
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PINCTRL_PIN(NOVO_NCA9539_GPIO6, "NCA9539_GPIO6"),
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PINCTRL_PIN(NOVO_NCA9539_GPIO7, "NCA9539_GPIO7"),
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PINCTRL_PIN(NOVO_NCA9539_GPIO8, "NCA9539_GPIO8"),
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PINCTRL_PIN(NOVO_NCA9539_GPIO9, "NCA9539_GPIO9"),
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PINCTRL_PIN(NOVO_NCA9539_GPIO10, "NCA9539_GPIO10"),
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PINCTRL_PIN(NOVO_NCA9539_GPIO11, "NCA9539_GPIO11"),
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PINCTRL_PIN(NOVO_NCA9539_GPIO12, "NCA9539_GPIO12"),
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PINCTRL_PIN(NOVO_NCA9539_GPIO13, "NCA9539_GPIO13"),
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PINCTRL_PIN(NOVO_NCA9539_GPIO14, "NCA9539_GPIO14"),
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PINCTRL_PIN(NOVO_NCA9539_GPIO15, "NCA9539_GPIO15"),
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};
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static struct group_desc nca9539_groups_desc[] = {
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GROUP_DESC(NCA9539_GPIO0),
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GROUP_DESC(NCA9539_GPIO1),
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GROUP_DESC(NCA9539_GPIO2),
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GROUP_DESC(NCA9539_GPIO3),
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GROUP_DESC(NCA9539_GPIO4),
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GROUP_DESC(NCA9539_GPIO5),
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GROUP_DESC(NCA9539_GPIO6),
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GROUP_DESC(NCA9539_GPIO7),
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GROUP_DESC(NCA9539_GPIO8),
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GROUP_DESC(NCA9539_GPIO9),
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GROUP_DESC(NCA9539_GPIO10),
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GROUP_DESC(NCA9539_GPIO11),
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GROUP_DESC(NCA9539_GPIO12),
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GROUP_DESC(NCA9539_GPIO13),
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GROUP_DESC(NCA9539_GPIO14),
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GROUP_DESC(NCA9539_GPIO15),
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};
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static struct function_desc nca9539_functions_desc[] = {
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FUNCTION_DESC_GPIO_INPUT(0),
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FUNCTION_DESC_GPIO_INPUT(1),
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FUNCTION_DESC_GPIO_INPUT(2),
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FUNCTION_DESC_GPIO_INPUT(3),
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FUNCTION_DESC_GPIO_INPUT(4),
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FUNCTION_DESC_GPIO_INPUT(5),
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FUNCTION_DESC_GPIO_INPUT(6),
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FUNCTION_DESC_GPIO_INPUT(7),
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FUNCTION_DESC_GPIO_INPUT(8),
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FUNCTION_DESC_GPIO_INPUT(9),
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FUNCTION_DESC_GPIO_INPUT(10),
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FUNCTION_DESC_GPIO_INPUT(11),
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FUNCTION_DESC_GPIO_INPUT(12),
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FUNCTION_DESC_GPIO_INPUT(13),
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FUNCTION_DESC_GPIO_INPUT(14),
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FUNCTION_DESC_GPIO_INPUT(15),
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FUNCTION_DESC_GPIO_OUTPUT(0),
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FUNCTION_DESC_GPIO_OUTPUT(1),
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FUNCTION_DESC_GPIO_OUTPUT(2),
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FUNCTION_DESC_GPIO_OUTPUT(3),
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FUNCTION_DESC_GPIO_OUTPUT(4),
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FUNCTION_DESC_GPIO_OUTPUT(5),
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FUNCTION_DESC_GPIO_OUTPUT(6),
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FUNCTION_DESC_GPIO_OUTPUT(7),
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FUNCTION_DESC_GPIO_OUTPUT(8),
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FUNCTION_DESC_GPIO_OUTPUT(9),
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FUNCTION_DESC_GPIO_OUTPUT(10),
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FUNCTION_DESC_GPIO_OUTPUT(11),
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FUNCTION_DESC_GPIO_OUTPUT(12),
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FUNCTION_DESC_GPIO_OUTPUT(13),
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FUNCTION_DESC_GPIO_OUTPUT(14),
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FUNCTION_DESC_GPIO_OUTPUT(15),
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};
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static struct serdes_chip_pinctrl_info nca9539_pinctrl_info = {
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.pins = nca9539_pins_desc,
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.num_pins = ARRAY_SIZE(nca9539_pins_desc),
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.groups = nca9539_groups_desc,
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.num_groups = ARRAY_SIZE(nca9539_groups_desc),
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.functions = nca9539_functions_desc,
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.num_functions = ARRAY_SIZE(nca9539_functions_desc),
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};
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static int nca9539_pinctrl_config_get(struct serdes *serdes,
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unsigned int pin, unsigned long *config)
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{
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return 0;
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}
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static int nca9539_pinctrl_config_set(struct serdes *serdes,
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unsigned int pin, unsigned long *configs,
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unsigned int num_configs)
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{
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return 0;
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}
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static int nca9539_pinctrl_set_mux(struct serdes *serdes,
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unsigned int function, unsigned int group)
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{
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return 0;
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}
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static struct serdes_chip_pinctrl_ops nca9539_pinctrl_ops = {
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.pin_config_get = nca9539_pinctrl_config_get,
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.pin_config_set = nca9539_pinctrl_config_set,
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.set_mux = nca9539_pinctrl_set_mux,
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};
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static int nca9539_gpio_direction_input(struct serdes *serdes, int gpio)
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{
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return 0;
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}
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static int nca9539_gpio_direction_output(struct serdes *serdes, int gpio, int value)
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{
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struct device *dev = serdes->dev;
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unsigned char port, pin, dir_reg, level_reg;
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int ret1 = 0, ret2 = 0;
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port = (gpio / 8) & 0x01;
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pin = (gpio % 8) & 0x7;
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dir_reg = (port == 0) ? REG_NCA9539_DIR_PORT0 : REG_NCA9539_DIR_PORT1;
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level_reg = (port == 0) ? REG_NCA9539_OUT_LEVEL_PORT0 : REG_NCA9539_OUT_LEVEL_PORT1;
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switch (pin) {
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case 0:
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ret1 = serdes_set_bits(serdes, dir_reg, BIT(0), FIELD_PREP(BIT(0), 0));
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ret2 = serdes_set_bits(serdes, level_reg, BIT(0), FIELD_PREP(BIT(0), value & 0x01));
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break;
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case 1:
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ret1 = serdes_set_bits(serdes, dir_reg, BIT(1), FIELD_PREP(BIT(1), 0));
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ret2 = serdes_set_bits(serdes, level_reg, BIT(1), FIELD_PREP(BIT(1), value & 0x01));
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break;
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case 2:
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ret1 = serdes_set_bits(serdes, dir_reg, BIT(2), FIELD_PREP(BIT(2), 0));
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ret2 = serdes_set_bits(serdes, level_reg, BIT(2), FIELD_PREP(BIT(2), value & 0x01));
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break;
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case 3:
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ret1 = serdes_set_bits(serdes, dir_reg, BIT(3), FIELD_PREP(BIT(3), 0));
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ret2 = serdes_set_bits(serdes, level_reg, BIT(3), FIELD_PREP(BIT(3), value & 0x01));
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break;
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case 4:
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ret1 = serdes_set_bits(serdes, dir_reg, BIT(4), FIELD_PREP(BIT(4), 0));
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ret2 = serdes_set_bits(serdes, level_reg, BIT(4), FIELD_PREP(BIT(4), value & 0x01));
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break;
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case 5:
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ret1 = serdes_set_bits(serdes, dir_reg, BIT(5), FIELD_PREP(BIT(5), 0));
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ret2 = serdes_set_bits(serdes, level_reg, BIT(5), FIELD_PREP(BIT(5), value & 0x01));
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break;
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case 6:
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ret1 = serdes_set_bits(serdes, dir_reg, BIT(6), FIELD_PREP(BIT(6), 0));
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ret2 = serdes_set_bits(serdes, level_reg, BIT(6), FIELD_PREP(BIT(6), value & 0x01));
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break;
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case 7:
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ret1 = serdes_set_bits(serdes, dir_reg, BIT(7), FIELD_PREP(BIT(7), 0));
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ret2 = serdes_set_bits(serdes, level_reg, BIT(7), FIELD_PREP(BIT(7), value & 0x01));
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break;
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default:
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break;
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}
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if (ret1 || ret2)
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dev_err(dev, "%s reg 0x%04x write error, pin=%d\n", __func__, level_reg, pin);
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return 0;
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}
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static int nca9539_gpio_get_level(struct serdes *serdes, int gpio)
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{
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return 0;
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}
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static int nca9539_gpio_set_level(struct serdes *serdes, int gpio, int value)
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{
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struct device *dev = serdes->dev;
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unsigned char port, pin, level_reg;
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int ret = 0;
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port = (gpio / 8) & 0x01;
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pin = (gpio % 8) & 0x7;
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level_reg = (port == 0) ? REG_NCA9539_OUT_LEVEL_PORT0 : REG_NCA9539_OUT_LEVEL_PORT1;
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switch (pin) {
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case 0:
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ret = serdes_set_bits(serdes, level_reg, BIT(0), FIELD_PREP(BIT(0), value & 0x01));
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break;
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case 1:
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ret = serdes_set_bits(serdes, level_reg, BIT(1), FIELD_PREP(BIT(1), value & 0x01));
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break;
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case 2:
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ret = serdes_set_bits(serdes, level_reg, BIT(2), FIELD_PREP(BIT(2), value & 0x01));
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break;
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case 3:
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ret = serdes_set_bits(serdes, level_reg, BIT(3), FIELD_PREP(BIT(3), value & 0x01));
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break;
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case 4:
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ret = serdes_set_bits(serdes, level_reg, BIT(4), FIELD_PREP(BIT(4), value & 0x01));
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break;
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case 5:
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ret = serdes_set_bits(serdes, level_reg, BIT(5), FIELD_PREP(BIT(5), value & 0x01));
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break;
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case 6:
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ret = serdes_set_bits(serdes, level_reg, BIT(6), FIELD_PREP(BIT(6), value & 0x01));
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break;
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case 7:
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ret = serdes_set_bits(serdes, level_reg, BIT(7), FIELD_PREP(BIT(7), value & 0x01));
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break;
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default:
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break;
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}
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if (ret)
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dev_err(dev, "%s reg 0x%04x write error, pin=%d\n", __func__, level_reg, pin);
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SERDES_DBG_CHIP("%s: serdes chip %s gpio=%d value=%d\n",
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__func__, serdes->chip_data->name, gpio, value);
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return 0;
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}
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static int nca9539_gpio_set_config(struct serdes *serdes, int gpio, unsigned long config)
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{
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return 0;
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}
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static int nca9539_gpio_to_irq(struct serdes *serdes, int gpio)
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{
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return 0;
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}
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static struct serdes_chip_gpio_ops nca9539_gpio_ops = {
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.direction_input = nca9539_gpio_direction_input,
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.direction_output = nca9539_gpio_direction_output,
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.get_level = nca9539_gpio_get_level,
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.set_level = nca9539_gpio_set_level,
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.set_config = nca9539_gpio_set_config,
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.to_irq = nca9539_gpio_to_irq,
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};
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static int nca9539_pm_suspend(struct serdes *serdes)
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{
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return 0;
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}
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static int nca9539_pm_resume(struct serdes *serdes)
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{
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return 0;
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}
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static struct serdes_chip_pm_ops nca9539_pm_ops = {
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.suspend = nca9539_pm_suspend,
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.resume = nca9539_pm_resume,
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};
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static int nca9539_irq_lock_handle(struct serdes *serdes)
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{
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return IRQ_HANDLED;
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}
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static int nca9539_irq_err_handle(struct serdes *serdes)
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{
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return IRQ_HANDLED;
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}
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static struct serdes_chip_irq_ops nca9539_irq_ops = {
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.lock_handle = nca9539_irq_lock_handle,
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.err_handle = nca9539_irq_err_handle,
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};
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struct serdes_chip_data serdes_nca9539_data = {
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.name = "nca9539",
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.serdes_type = TYPE_OTHER,
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.serdes_id = NOVO_ID_NCA9539,
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.sequence_init = 1,
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.regmap_config = &nca9539_regmap_config,
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.pinctrl_info = &nca9539_pinctrl_info,
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.pinctrl_ops = &nca9539_pinctrl_ops,
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.gpio_ops = &nca9539_gpio_ops,
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.pm_ops = &nca9539_pm_ops,
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.irq_ops = &nca9539_irq_ops,
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};
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EXPORT_SYMBOL_GPL(serdes_nca9539_data);
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MODULE_LICENSE("GPL");
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