/*
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* Copyright (C) 2021 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <power/rk8xx_pmic.h>
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#include <power/pmic.h>
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#include <power/regulator.h>
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#ifndef CONFIG_SPL_BUILD
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#define ENABLE_DRIVER
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#endif
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/* Not used or exisit register and configure */
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#define NA -1
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/* rk806 buck*/
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#define RK806_BUCK_ON_VSEL(n) (0x1a + n - 1)
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#define RK806_BUCK_SLP_VSEL(n) (0x24 + n - 1)
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#define RK806_BUCK_CONFIG(n) (0x10 + n - 1)
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#define RK806_BUCK_VSEL_MASK 0xff
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/* RK806 LDO */
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#define RK806_NLDO_ON_VSEL(n) (0x43 + n - 1)
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#define RK806_NLDO_SLP_VSEL(n) (0x48 + n - 1)
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#define RK806_NLDO_VSEL_MASK 0xff
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#define RK806_PLDO_ON_VSEL(n) (0x4e + n - 1)
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#define RK806_PLDO_SLP_VSEL(n) (0x54 + n - 1)
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#define RK806_PLDO_VSEL_MASK 0xff
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/* RK806 ENABLE */
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#define RK806_POWER_EN(n) (0x00 + n)
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#define RK806_NLDO_EN(n) (0x03 + n)
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#define RK806_PLDO_EN(n) (0x04 + n)
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#define RK806_BUCK_SUSPEND_EN 0x06
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#define RK806_NLDO_SUSPEND_EN 0x07
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#define RK806_PLDO_SUSPEND_EN 0x08
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#define RK806_RAMP_RATE_MASK1 0xc0
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#define RK806_RAMP_RATE_REG1(n) (0x10 + n)
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#define RK806_RAMP_RATE_REG1_8 0xeb
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#define RK806_RAMP_RATE_REG9_10 0xea
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#define RK806_RAMP_RATE_4LSB_PER_1CLK 0x00/* LDO 100mV/uS buck 50mV/us */
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#define RK806_RAMP_RATE_2LSB_PER_1CLK 0x01/* LDO 50mV/uS buck 25mV/us */
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#define RK806_RAMP_RATE_1LSB_PER_1CLK 0x02/* LDO 25mV/uS buck 12.5mV/us */
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#define RK806_RAMP_RATE_1LSB_PER_2CLK 0x03/* LDO 12.5mV/uS buck 6.25mV/us */
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#define RK806_RAMP_RATE_1LSB_PER_4CLK 0x04/* LDO 6.28/2mV/uS buck 3.125mV/us */
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#define RK806_RAMP_RATE_1LSB_PER_8CLK 0x05/* LDO 3.12mV/uS buck 1.56mV/us */
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#define RK806_RAMP_RATE_1LSB_PER_13CLK 0x06/* LDO 1.9mV/uS buck 961mV/us */
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#define RK806_RAMP_RATE_1LSB_PER_32CLK 0x07/* LDO 0.78mV/uS buck 0.39mV/us */
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#define RK806_PLDO0_2_MSK(pldo) (BIT(pldo + 5))
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#define RK806_PLDO0_2_SET(pldo) (BIT(pldo + 1) | RK806_PLDO0_2_MSK(pldo))
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#define RK806_PLDO0_2_CLR(pldo) RK806_PLDO0_2_MSK(pldo)
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struct rk8xx_reg_info {
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uint min_uv;
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uint step_uv;
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u8 vsel_reg;
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u8 vsel_sleep_reg;
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u8 config_reg;
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u8 vsel_mask;
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u8 min_sel;
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/* only for buck now */
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u8 max_sel;
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u8 range_num;
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};
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static const struct rk8xx_reg_info rk806_buck[] = {
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/* buck 1 */
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{ 500000, 6250, RK806_BUCK_ON_VSEL(1), RK806_BUCK_SLP_VSEL(1), RK806_BUCK_CONFIG(1), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3},
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{ 1500000, 25000, RK806_BUCK_ON_VSEL(1), RK806_BUCK_SLP_VSEL(1), RK806_BUCK_CONFIG(1), RK806_BUCK_VSEL_MASK, 0xa0, 0xec, 3},
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{ 3400000, 0, RK806_BUCK_ON_VSEL(1), RK806_BUCK_SLP_VSEL(1), RK806_BUCK_CONFIG(1), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3},
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/* buck 2 */
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{ 500000, 6250, RK806_BUCK_ON_VSEL(2), RK806_BUCK_SLP_VSEL(2), RK806_BUCK_CONFIG(2), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3},
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{ 1500000, 25000, RK806_BUCK_ON_VSEL(2), RK806_BUCK_SLP_VSEL(2), RK806_BUCK_CONFIG(2), RK806_BUCK_VSEL_MASK, 0xa0, 0xed, 3},
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{ 3400000, 0, RK806_BUCK_ON_VSEL(2), RK806_BUCK_SLP_VSEL(2), RK806_BUCK_CONFIG(2), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3},
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/* buck 3 */
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{ 500000, 6250, RK806_BUCK_ON_VSEL(3), RK806_BUCK_SLP_VSEL(3), RK806_BUCK_CONFIG(3), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3},
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{ 1500000, 25000, RK806_BUCK_ON_VSEL(3), RK806_BUCK_SLP_VSEL(3), RK806_BUCK_CONFIG(3), RK806_BUCK_VSEL_MASK, 0xa0, 0xed, 3},
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{ 3400000, 0, RK806_BUCK_ON_VSEL(3), RK806_BUCK_SLP_VSEL(3), RK806_BUCK_CONFIG(3), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3},
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/* buck 4 */
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{ 500000, 6250, RK806_BUCK_ON_VSEL(4), RK806_BUCK_SLP_VSEL(4), RK806_BUCK_CONFIG(4), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3},
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{ 1500000, 25000, RK806_BUCK_ON_VSEL(4), RK806_BUCK_SLP_VSEL(4), RK806_BUCK_CONFIG(4), RK806_BUCK_VSEL_MASK, 0xa0, 0xed, 3},
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{ 3400000, 0, RK806_BUCK_ON_VSEL(4), RK806_BUCK_SLP_VSEL(4), RK806_BUCK_CONFIG(4), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3},
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/* buck 5 */
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{ 500000, 6250, RK806_BUCK_ON_VSEL(5), RK806_BUCK_SLP_VSEL(5), RK806_BUCK_CONFIG(5), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3},
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{ 1500000, 25000, RK806_BUCK_ON_VSEL(5), RK806_BUCK_SLP_VSEL(5), RK806_BUCK_CONFIG(5), RK806_BUCK_VSEL_MASK, 0xa0, 0xed, 3},
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{ 3400000, 0, RK806_BUCK_ON_VSEL(5), RK806_BUCK_SLP_VSEL(5), RK806_BUCK_CONFIG(5), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3},
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/* buck 6 */
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{ 500000, 6250, RK806_BUCK_ON_VSEL(6), RK806_BUCK_SLP_VSEL(6), RK806_BUCK_CONFIG(6), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3},
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{ 1500000, 25000, RK806_BUCK_ON_VSEL(6), RK806_BUCK_SLP_VSEL(6), RK806_BUCK_CONFIG(6), RK806_BUCK_VSEL_MASK, 0xa0, 0xed, 3},
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{ 3400000, 0, RK806_BUCK_ON_VSEL(6), RK806_BUCK_SLP_VSEL(6), RK806_BUCK_CONFIG(6), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3},
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/* buck 7 */
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{ 500000, 6250, RK806_BUCK_ON_VSEL(7), RK806_BUCK_SLP_VSEL(7), RK806_BUCK_CONFIG(7), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3},
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{ 1500000, 25000, RK806_BUCK_ON_VSEL(7), RK806_BUCK_SLP_VSEL(7), RK806_BUCK_CONFIG(7), RK806_BUCK_VSEL_MASK, 0xa0, 0xed, 3},
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{ 3400000, 0, RK806_BUCK_ON_VSEL(7), RK806_BUCK_SLP_VSEL(7), RK806_BUCK_CONFIG(7), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3},
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/* buck 8 */
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{ 500000, 6250, RK806_BUCK_ON_VSEL(8), RK806_BUCK_SLP_VSEL(8), RK806_BUCK_CONFIG(8), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3},
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{ 1500000, 25000, RK806_BUCK_ON_VSEL(8), RK806_BUCK_SLP_VSEL(8), RK806_BUCK_CONFIG(8), RK806_BUCK_VSEL_MASK, 0xa0, 0xed, 3},
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{ 3400000, 0, RK806_BUCK_ON_VSEL(8), RK806_BUCK_SLP_VSEL(8), RK806_BUCK_CONFIG(8), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3},
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/* buck 9 */
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{ 500000, 6250, RK806_BUCK_ON_VSEL(9), RK806_BUCK_SLP_VSEL(9), RK806_BUCK_CONFIG(9), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3},
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{ 1500000, 25000, RK806_BUCK_ON_VSEL(9), RK806_BUCK_SLP_VSEL(9), RK806_BUCK_CONFIG(9), RK806_BUCK_VSEL_MASK, 0xa0, 0xed, 3},
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{ 3400000, 0, RK806_BUCK_ON_VSEL(9), RK806_BUCK_SLP_VSEL(9), RK806_BUCK_CONFIG(9), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3},
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/* buck 10 */
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{ 500000, 6250, RK806_BUCK_ON_VSEL(10), RK806_BUCK_SLP_VSEL(10), RK806_BUCK_CONFIG(10), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3},
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{ 1500000, 25000, RK806_BUCK_ON_VSEL(10), RK806_BUCK_SLP_VSEL(10), RK806_BUCK_CONFIG(10), RK806_BUCK_VSEL_MASK, 0xa0, 0xed, 3},
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{ 3400000, 0, RK806_BUCK_ON_VSEL(10), RK806_BUCK_SLP_VSEL(10), RK806_BUCK_CONFIG(10), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3},
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};
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static const struct rk8xx_reg_info rk806_nldo[] = {
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/* nldo1 */
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{ 500000, 12500, RK806_NLDO_ON_VSEL(1), RK806_NLDO_SLP_VSEL(1), NA, RK806_NLDO_VSEL_MASK, 0x00, },
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{ 3400000, 0, RK806_NLDO_ON_VSEL(1), RK806_NLDO_SLP_VSEL(1), NA, RK806_NLDO_VSEL_MASK, 0xE8, },
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/* nldo2 */
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{ 500000, 12500, RK806_NLDO_ON_VSEL(2), RK806_NLDO_SLP_VSEL(2), NA, RK806_NLDO_VSEL_MASK, 0x00, },
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{ 3400000, 0, RK806_NLDO_ON_VSEL(2), RK806_NLDO_SLP_VSEL(2), NA, RK806_NLDO_VSEL_MASK, 0xE8, },
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/* nldo3 */
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{ 500000, 12500, RK806_NLDO_ON_VSEL(3), RK806_NLDO_SLP_VSEL(3), NA, RK806_NLDO_VSEL_MASK, 0x00, },
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{ 3400000, 0, RK806_NLDO_ON_VSEL(3), RK806_NLDO_SLP_VSEL(3), NA, RK806_NLDO_VSEL_MASK, 0xE8, },
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/* nldo4 */
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{ 500000, 12500, RK806_NLDO_ON_VSEL(4), RK806_NLDO_SLP_VSEL(4), NA, RK806_NLDO_VSEL_MASK, 0x00, },
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{ 3400000, 0, RK806_NLDO_ON_VSEL(4), RK806_NLDO_SLP_VSEL(4), NA, RK806_NLDO_VSEL_MASK, 0xE8, },
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/* nldo5 */
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{ 500000, 12500, RK806_NLDO_ON_VSEL(5), RK806_NLDO_SLP_VSEL(5), NA, RK806_NLDO_VSEL_MASK, 0x00, },
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{ 3400000, 0, RK806_NLDO_ON_VSEL(5), RK806_NLDO_SLP_VSEL(5), NA, RK806_NLDO_VSEL_MASK, 0xE8, },
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};
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static const struct rk8xx_reg_info rk806_pldo[] = {
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/* pldo1 */
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{ 500000, 12500, RK806_PLDO_ON_VSEL(1), RK806_PLDO_SLP_VSEL(1), NA, RK806_PLDO_VSEL_MASK, 0x00, },
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{ 3400000, 0, RK806_PLDO_ON_VSEL(1), RK806_PLDO_SLP_VSEL(1), NA, RK806_PLDO_VSEL_MASK, 0xE8, },
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/* pldo2 */
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{ 500000, 12500, RK806_PLDO_ON_VSEL(2), RK806_PLDO_SLP_VSEL(2), NA, RK806_PLDO_VSEL_MASK, 0x00, },
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{ 3400000, 0, RK806_PLDO_ON_VSEL(2), RK806_PLDO_SLP_VSEL(2), NA, RK806_PLDO_VSEL_MASK, 0xE8, },
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/* pldo3 */
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{ 500000, 12500, RK806_PLDO_ON_VSEL(3), RK806_PLDO_SLP_VSEL(3), NA, RK806_PLDO_VSEL_MASK, 0x00, },
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{ 3400000, 0, RK806_PLDO_ON_VSEL(3), RK806_PLDO_SLP_VSEL(3), NA, RK806_PLDO_VSEL_MASK, 0xE8, },
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/* pldo4 */
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{ 500000, 12500, RK806_PLDO_ON_VSEL(4), RK806_PLDO_SLP_VSEL(4), NA, RK806_PLDO_VSEL_MASK, 0x00, },
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{ 3400000, 0, RK806_PLDO_ON_VSEL(4), RK806_PLDO_SLP_VSEL(4), NA, RK806_PLDO_VSEL_MASK, 0xE8, },
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/* pldo5 */
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{ 500000, 12500, RK806_PLDO_ON_VSEL(5), RK806_PLDO_SLP_VSEL(5), NA, RK806_PLDO_VSEL_MASK, 0x00, },
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{ 3400000, 0, RK806_PLDO_ON_VSEL(5), RK806_PLDO_SLP_VSEL(5), NA, RK806_PLDO_VSEL_MASK, 0xE8, },
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/* pldo6 */
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{ 500000, 12500, RK806_PLDO_ON_VSEL(6), RK806_PLDO_SLP_VSEL(6), NA, RK806_PLDO_VSEL_MASK, 0x00, },
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{ 3400000, 0, RK806_PLDO_ON_VSEL(6), RK806_PLDO_SLP_VSEL(6), NA, RK806_PLDO_VSEL_MASK, 0xE8, },
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};
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static const struct rk8xx_reg_info *get_buck_reg(struct udevice *pmic,
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int num, int uvolt)
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{
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struct rk8xx_priv *priv = dev_get_priv(pmic);
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switch (priv->variant) {
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case RK806_ID:
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switch (num) {
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case 0 ... 9:
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if (uvolt < 1500000)
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return &rk806_buck[num * 3 + 0];
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else if (uvolt < 3400000)
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return &rk806_buck[num * 3 + 1];
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else
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return &rk806_buck[num * 3 + 2];
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break;
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}
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default:
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return &rk806_buck[num * 3 + 0];
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}
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}
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static int _buck_set_value(struct udevice *pmic, int buck, int uvolt)
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{
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const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, uvolt);
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int mask = info->vsel_mask;
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int val;
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if (info->vsel_reg == NA)
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return -EINVAL;
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if (info->step_uv == 0) /* Fixed voltage */
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val = info->min_sel;
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else
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val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel;
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debug("%s: volt=%d, buck=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
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__func__, uvolt, buck + 1, info->vsel_reg, mask, val);
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return pmic_clrsetbits(pmic, info->vsel_reg, mask, val);
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}
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static int _buck_set_enable(struct udevice *pmic, int buck, bool enable)
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{
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struct rk8xx_priv *priv = dev_get_priv(pmic);
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uint value, en_reg;
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int ret;
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switch (priv->variant) {
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case RK806_ID:
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en_reg = RK806_POWER_EN(buck / 4);
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if (enable)
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value = ((1 << buck % 4) | (1 << (buck % 4 + 4)));
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else
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value = ((0 << buck % 4) | (1 << (buck % 4 + 4)));
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ret = pmic_reg_write(pmic, en_reg, value);
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break;
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default:
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ret = -EINVAL;
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}
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return ret;
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}
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#ifdef ENABLE_DRIVER
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static int _buck_set_suspend_value(struct udevice *pmic, int buck, int uvolt)
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{
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const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, uvolt);
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int mask = info->vsel_mask;
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int val;
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if (info->vsel_sleep_reg == NA)
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return -EINVAL;
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if (info->step_uv == 0)
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val = info->min_sel;
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else
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val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel;
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debug("%s: volt=%d, buck=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
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__func__, uvolt, buck + 1, info->vsel_sleep_reg, mask, val);
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return pmic_clrsetbits(pmic, info->vsel_sleep_reg, mask, val);
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}
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static int _buck_get_enable(struct udevice *pmic, int buck)
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{
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struct rk8xx_priv *priv = dev_get_priv(pmic);
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uint mask = 0;
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int ret = 0;
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switch (priv->variant) {
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case RK806_ID:
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mask = 1 << buck % 4;
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ret = pmic_reg_read(pmic, RK806_POWER_EN(buck / 4));
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break;
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default:
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ret = 0;
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}
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if (ret < 0)
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return ret;
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return ret & mask ? true : false;
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}
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static int _buck_set_ramp_delay(struct udevice *pmic, int buck, u32 ramp_delay)
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{
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const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, 0);
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struct rk8xx_priv *priv = dev_get_priv(pmic);
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int ramp_value = 0, reg_value;
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int ramp_reg1, ramp_reg2;
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if (info->config_reg == NA)
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return -EINVAL;
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switch (priv->variant) {
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case RK806_ID:
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switch (ramp_delay) {
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case 1 ... 390:
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ramp_value = RK806_RAMP_RATE_1LSB_PER_32CLK;
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break;
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case 391 ... 961:
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ramp_value = RK806_RAMP_RATE_1LSB_PER_13CLK;
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break;
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case 962 ... 1560:
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ramp_value = RK806_RAMP_RATE_1LSB_PER_8CLK;
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break;
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case 1561 ... 3125:
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ramp_value = RK806_RAMP_RATE_1LSB_PER_4CLK;
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break;
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case 3126 ... 6250:
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ramp_value = RK806_RAMP_RATE_1LSB_PER_2CLK;
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break;
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case 6251 ... 12500:
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ramp_value = RK806_RAMP_RATE_1LSB_PER_1CLK;
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break;
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case 12501 ... 25000:
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ramp_value = RK806_RAMP_RATE_2LSB_PER_1CLK;
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break;
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case 25001 ... 50000: /* 50mV/us */
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ramp_value = RK806_RAMP_RATE_4LSB_PER_1CLK;
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break;
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default:
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ramp_value = RK806_RAMP_RATE_1LSB_PER_32CLK;
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printf("buck%d ramp_delay: %d not supported\n",
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buck, ramp_delay);
|
break;
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}
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break;
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default:
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ramp_value = RK806_RAMP_RATE_1LSB_PER_32CLK;
|
return -EINVAL;
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}
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ramp_reg1 = RK806_RAMP_RATE_REG1(buck);
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if (buck < 8)
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ramp_reg2 = RK806_RAMP_RATE_REG1_8;
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else
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ramp_reg2 = RK806_RAMP_RATE_REG9_10;
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reg_value = pmic_reg_read(pmic, ramp_reg1);
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if (reg_value < 0) {
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printf("buck%d read ramp reg(0x%x) error: %d", buck, ramp_reg1, reg_value);
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return reg_value;
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}
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reg_value &= 0x3f;
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pmic_reg_write(pmic,
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ramp_reg1,
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reg_value | (ramp_value & 0x03) << 0x06);
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reg_value = pmic_reg_read(pmic, ramp_reg2);
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if (reg_value < 0) {
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printf("buck%d read ramp reg(0x%x) error: %d", buck, ramp_reg2, reg_value);
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return reg_value;
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}
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return pmic_reg_write(pmic,
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ramp_reg2,
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reg_value | (ramp_value & 0x04) << (buck % 8));
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}
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static int _buck_set_suspend_enable(struct udevice *pmic, int buck, bool enable)
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{
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uint mask;
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int ret;
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|
if (buck <= 7) {
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mask = 1 << buck;
|
ret = pmic_clrsetbits(pmic, RK806_BUCK_SUSPEND_EN, mask,
|
enable ? mask : 0);
|
} else {
|
if (buck == 8)
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mask = 0x40;
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else
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mask = 0x80;
|
ret = pmic_clrsetbits(pmic, RK806_NLDO_SUSPEND_EN, mask,
|
enable ? mask : 0);
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}
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|
return ret;
|
}
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|
static int _buck_get_suspend_enable(struct udevice *pmic, int buck)
|
{
|
uint mask, val;
|
int ret;
|
|
if (buck <= 7) {
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mask = 1 << buck % 7;
|
val = pmic_reg_read(pmic, RK806_BUCK_SUSPEND_EN);
|
} else {
|
mask = 1 << ((buck - 7) + 6);
|
val = pmic_reg_read(pmic, RK806_NLDO_SUSPEND_EN);
|
}
|
|
if (val < 0)
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return val;
|
ret = val & mask ? 1 : 0;
|
|
return ret;
|
}
|
|
static const struct rk8xx_reg_info *get_ldo_reg(struct udevice *pmic,
|
int num, int uvolt)
|
{
|
struct rk8xx_priv *priv = dev_get_priv(pmic);
|
|
switch (priv->variant) {
|
case RK806_ID:
|
if (uvolt < 3400000)
|
return &rk806_nldo[num * 2];
|
else
|
return &rk806_nldo[num * 2 + 1];
|
default:
|
return &rk806_nldo[num * 2];
|
}
|
}
|
|
static const struct rk8xx_reg_info *get_pldo_reg(struct udevice *pmic,
|
int num, int uvolt)
|
{
|
struct rk8xx_priv *priv = dev_get_priv(pmic);
|
|
switch (priv->variant) {
|
case RK806_ID:
|
if (uvolt < 3400000)
|
return &rk806_pldo[num * 2];
|
else
|
return &rk806_pldo[num * 2 + 1];
|
default:
|
return &rk806_pldo[num * 2];
|
}
|
}
|
|
static int _ldo_get_enable(struct udevice *pmic, int ldo)
|
{
|
struct rk8xx_priv *priv = dev_get_priv(pmic);
|
uint mask = 0;
|
int ret = 0;
|
|
switch (priv->variant) {
|
case RK806_ID:
|
if (ldo < 4) {
|
mask = 1 << ldo % 4;
|
ret = pmic_reg_read(pmic, RK806_NLDO_EN(ldo / 4));
|
} else {
|
mask = 1 << 2;
|
ret = pmic_reg_read(pmic, RK806_NLDO_EN(2));
|
}
|
break;
|
default:
|
return false;
|
}
|
|
if (ret < 0)
|
return ret;
|
|
return ret & mask ? true : false;
|
}
|
|
static int _ldo_set_enable(struct udevice *pmic, int ldo, bool enable)
|
{
|
struct rk8xx_priv *priv = dev_get_priv(pmic);
|
uint value, en_reg;
|
int ret = 0;
|
|
switch (priv->variant) {
|
case RK806_ID:
|
if (ldo < 4) {
|
en_reg = RK806_NLDO_EN(0);
|
if (enable)
|
value = ((1 << ldo % 4) | (1 << (ldo % 4 + 4)));
|
else
|
value = ((0 << ldo % 4) | (1 << (ldo % 4 + 4)));
|
ret = pmic_reg_write(pmic, en_reg, value);
|
} else {
|
en_reg = RK806_NLDO_EN(2);
|
if (enable)
|
value = 0x44;
|
else
|
value = 0x40;
|
ret = pmic_reg_write(pmic, en_reg, value);
|
}
|
break;
|
default:
|
return -EINVAL;
|
}
|
|
return ret;
|
}
|
|
static int _pldo_get_enable(struct udevice *pmic, int pldo)
|
{
|
struct rk8xx_priv *priv = dev_get_priv(pmic);
|
uint mask = 0, en_reg;
|
int ret = 0;
|
|
switch (priv->variant) {
|
case RK806_ID:
|
if ((pldo < 3) || (pldo == 5)) {
|
en_reg = RK806_PLDO_EN(0);
|
mask = RK806_PLDO0_2_SET(pldo);
|
if (pldo == 5)
|
mask = (1 << 0);
|
ret = pmic_reg_read(pmic, en_reg);
|
} else if ((pldo == 3) || (pldo == 4)) {
|
en_reg = RK806_PLDO_EN(1);
|
if (pldo == 3)
|
mask = (1 << 0);
|
else
|
mask = (1 << 1);
|
ret = pmic_reg_read(pmic, en_reg);
|
}
|
break;
|
|
default:
|
return -EINVAL;
|
}
|
|
if (ret < 0)
|
return ret;
|
|
return ret & mask ? true : false;
|
}
|
|
static int _pldo_set_enable(struct udevice *pmic, int pldo, bool enable)
|
{
|
struct rk8xx_priv *priv = dev_get_priv(pmic);
|
uint value, en_reg;
|
int ret = 0;
|
|
switch (priv->variant) {
|
case RK806_ID:
|
if (pldo < 3) {
|
en_reg = RK806_PLDO_EN(0);
|
if (enable)
|
value = RK806_PLDO0_2_SET(pldo);
|
else
|
value = RK806_PLDO0_2_CLR(pldo);
|
ret = pmic_reg_write(pmic, en_reg, value);
|
} else if (pldo == 3) {
|
en_reg = RK806_PLDO_EN(1);
|
if (enable)
|
value = ((1 << 0) | (1 << 4));
|
else
|
value = (1 << 4);
|
ret = pmic_reg_write(pmic, en_reg, value);
|
} else if (pldo == 4) {
|
en_reg = RK806_PLDO_EN(1);
|
if (enable)
|
value = ((1 << 1) | (1 << 5));
|
else
|
value = ((0 << 1) | (1 << 5));
|
ret = pmic_reg_write(pmic, en_reg, value);
|
} else if (pldo == 5) {
|
en_reg = RK806_PLDO_EN(0);
|
if (enable)
|
value = ((1 << 0) | (1 << 4));
|
else
|
value = ((0 << 0) | (1 << 4));
|
ret = pmic_reg_write(pmic, en_reg, value);
|
}
|
|
break;
|
default:
|
return -EINVAL;
|
}
|
|
return ret;
|
}
|
|
static int _ldo_set_suspend_enable(struct udevice *pmic, int ldo, bool enable)
|
{
|
uint mask;
|
int ret;
|
|
mask = 1 << ldo;
|
ret = pmic_clrsetbits(pmic, RK806_NLDO_SUSPEND_EN, mask,
|
enable ? mask : 0);
|
|
return ret;
|
}
|
|
static int _ldo_get_suspend_enable(struct udevice *pmic, int ldo)
|
{
|
uint mask, val;
|
int ret;
|
|
mask = 1 << ldo;
|
val = pmic_reg_read(pmic, RK806_NLDO_SUSPEND_EN);
|
|
if (val < 0)
|
return val;
|
ret = val & mask ? 1 : 0;
|
|
return ret;
|
}
|
|
static int buck_get_value(struct udevice *dev)
|
{
|
int buck = dev->driver_data - 1;
|
const struct rk8xx_reg_info *info = get_buck_reg(dev->parent, buck, 0);
|
int mask = info->vsel_mask;
|
int i, ret, val;
|
|
if (info->vsel_reg == NA)
|
return -EINVAL;
|
|
ret = pmic_reg_read(dev->parent, info->vsel_reg);
|
if (ret < 0)
|
return ret;
|
|
val = ret & mask;
|
if (val >= info->min_sel && val <= info->max_sel)
|
goto finish;
|
|
/* unlucky to try */
|
for (i = 1; i < info->range_num; i++) {
|
info++;
|
if (val <= info->max_sel && val >= info->min_sel)
|
break;
|
}
|
|
finish:
|
return info->min_uv + (val - info->min_sel) * info->step_uv;
|
}
|
|
static int buck_set_value(struct udevice *dev, int uvolt)
|
{
|
int buck = dev->driver_data - 1;
|
|
return _buck_set_value(dev->parent, buck, uvolt);
|
}
|
|
static int buck_get_suspend_value(struct udevice *dev)
|
{
|
int buck = dev->driver_data - 1;
|
const struct rk8xx_reg_info *info = get_buck_reg(dev->parent, buck, 0);
|
int mask = info->vsel_mask;
|
int i, ret, val;
|
|
if (info->vsel_sleep_reg == NA)
|
return -EINVAL;
|
|
ret = pmic_reg_read(dev->parent, info->vsel_sleep_reg);
|
if (ret < 0)
|
return ret;
|
|
val = ret & mask;
|
if (val <= info->max_sel && val >= info->min_sel)
|
goto finish;
|
|
/* unlucky to try */
|
for (i = 1; i < info->range_num; i++) {
|
info++;
|
if (val <= info->max_sel && val >= info->min_sel)
|
break;
|
}
|
|
finish:
|
return info->min_uv + (val - info->min_sel) * info->step_uv;
|
}
|
|
static int buck_set_suspend_value(struct udevice *dev, int uvolt)
|
{
|
int buck = dev->driver_data - 1;
|
|
return _buck_set_suspend_value(dev->parent, buck, uvolt);
|
}
|
|
static int buck_set_enable(struct udevice *dev, bool enable)
|
{
|
int buck = dev->driver_data - 1;
|
|
return _buck_set_enable(dev->parent, buck, enable);
|
}
|
|
static int buck_set_suspend_enable(struct udevice *dev, bool enable)
|
{
|
int buck = dev->driver_data - 1;
|
|
return _buck_set_suspend_enable(dev->parent, buck, enable);
|
}
|
|
static int buck_get_suspend_enable(struct udevice *dev)
|
{
|
int buck = dev->driver_data - 1;
|
|
return _buck_get_suspend_enable(dev->parent, buck);
|
}
|
|
static int buck_set_ramp_delay(struct udevice *dev, u32 ramp_delay)
|
{
|
int buck = dev->driver_data - 1;
|
|
return _buck_set_ramp_delay(dev->parent, buck, ramp_delay);
|
}
|
|
static int buck_get_enable(struct udevice *dev)
|
{
|
int buck = dev->driver_data - 1;
|
|
return _buck_get_enable(dev->parent, buck);
|
}
|
|
static int ldo_get_value(struct udevice *dev)
|
{
|
int ldo = dev->driver_data - 1;
|
const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, 0);
|
int mask = info->vsel_mask;
|
int ret, val;
|
|
if (info->vsel_reg == NA)
|
return -EINVAL;
|
|
ret = pmic_reg_read(dev->parent, info->vsel_reg);
|
if (ret < 0)
|
return ret;
|
val = ret & mask;
|
|
return info->min_uv + val * info->step_uv;
|
}
|
|
static int ldo_set_value(struct udevice *dev, int uvolt)
|
{
|
int ldo = dev->driver_data - 1;
|
const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, uvolt);
|
int mask = info->vsel_mask;
|
int val;
|
|
if (info->vsel_reg == NA)
|
return -EINVAL;
|
|
if (info->step_uv == 0)
|
val = info->min_sel;
|
else
|
val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel;
|
|
debug("%s: volt=%d, ldo=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
|
__func__, uvolt, ldo + 1, info->vsel_reg, mask, val);
|
|
return pmic_clrsetbits(dev->parent, info->vsel_reg, mask, val);
|
}
|
|
static int pldo_get_value(struct udevice *dev)
|
{
|
int ldo = dev->driver_data - 1;
|
const struct rk8xx_reg_info *info = get_pldo_reg(dev->parent, ldo, 0);
|
int mask = info->vsel_mask;
|
int ret, val;
|
|
if (info->vsel_reg == NA)
|
return -EINVAL;
|
|
ret = pmic_reg_read(dev->parent, info->vsel_reg);
|
if (ret < 0)
|
return ret;
|
val = ret & mask;
|
|
return info->min_uv + val * info->step_uv;
|
}
|
|
static int pldo_set_value(struct udevice *dev, int uvolt)
|
{
|
int ldo = dev->driver_data - 1;
|
const struct rk8xx_reg_info *info = get_pldo_reg(dev->parent, ldo, uvolt);
|
int mask = info->vsel_mask;
|
int val;
|
|
if (info->vsel_reg == NA)
|
return -EINVAL;
|
|
if (info->step_uv == 0)
|
val = info->min_sel;
|
else
|
val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel;
|
|
debug("%s: volt=%d, ldo=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
|
__func__, uvolt, ldo + 1, info->vsel_reg, mask, val);
|
|
return pmic_clrsetbits(dev->parent, info->vsel_reg, mask, val);
|
}
|
|
static int ldo_set_suspend_value(struct udevice *dev, int uvolt)
|
{
|
int ldo = dev->driver_data - 1;
|
const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, uvolt);
|
int mask = info->vsel_mask;
|
int val;
|
|
if (info->vsel_sleep_reg == NA)
|
return -EINVAL;
|
|
if (info->step_uv == 0)
|
val = info->min_sel;
|
else
|
val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel;
|
|
debug("%s: volt=%d, ldo=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
|
__func__, uvolt, ldo + 1, info->vsel_sleep_reg, mask, val);
|
|
return pmic_clrsetbits(dev->parent, info->vsel_sleep_reg, mask, val);
|
}
|
|
static int ldo_get_suspend_value(struct udevice *dev)
|
{
|
int ldo = dev->driver_data - 1;
|
const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, 0);
|
int mask = info->vsel_mask;
|
int val, ret;
|
|
if (info->vsel_sleep_reg == NA)
|
return -EINVAL;
|
|
ret = pmic_reg_read(dev->parent, info->vsel_sleep_reg);
|
if (ret < 0)
|
return ret;
|
|
val = ret & mask;
|
|
return info->min_uv + val * info->step_uv;
|
}
|
|
static int ldo_set_enable(struct udevice *dev, bool enable)
|
{
|
int ldo = dev->driver_data - 1;
|
|
return _ldo_set_enable(dev->parent, ldo, enable);
|
}
|
|
static int ldo_set_suspend_enable(struct udevice *dev, bool enable)
|
{
|
int ldo = dev->driver_data - 1;
|
|
return _ldo_set_suspend_enable(dev->parent, ldo, enable);
|
}
|
|
static int ldo_get_suspend_enable(struct udevice *dev)
|
{
|
int ldo = dev->driver_data - 1;
|
|
return _ldo_get_suspend_enable(dev->parent, ldo);
|
}
|
|
static int ldo_get_enable(struct udevice *dev)
|
{
|
int ldo = dev->driver_data - 1;
|
|
return _ldo_get_enable(dev->parent, ldo);
|
}
|
|
static int pldo_set_enable(struct udevice *dev, bool enable)
|
{
|
int ldo = dev->driver_data - 1;
|
|
return _pldo_set_enable(dev->parent, ldo, enable);
|
}
|
|
static int pldo_get_enable(struct udevice *dev)
|
{
|
int ldo = dev->driver_data - 1;
|
|
return _pldo_get_enable(dev->parent, ldo);
|
}
|
|
static int pldo_set_suspend_value(struct udevice *dev, int uvolt)
|
{
|
int ldo = dev->driver_data - 1;
|
const struct rk8xx_reg_info *info = get_pldo_reg(dev->parent, ldo, uvolt);;
|
int mask = info->vsel_mask;
|
int val;
|
|
if (info->vsel_sleep_reg == NA)
|
return -EINVAL;
|
|
if (info->step_uv == 0)
|
val = info->min_sel;
|
else
|
val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel;
|
|
return pmic_clrsetbits(dev->parent, info->vsel_sleep_reg, mask, val);
|
}
|
|
static int pldo_get_suspend_value(struct udevice *dev)
|
{
|
int ldo = dev->driver_data - 1;
|
const struct rk8xx_reg_info *info = get_pldo_reg(dev->parent, ldo, 0);
|
int mask = info->vsel_mask;
|
int val, ret;
|
|
if (info->vsel_sleep_reg == NA)
|
return -EINVAL;
|
|
ret = pmic_reg_read(dev->parent, info->vsel_sleep_reg);
|
if (ret < 0)
|
return ret;
|
|
val = ret & mask;
|
|
return info->min_uv + val * info->step_uv;
|
}
|
|
static int _pldo_set_suspend_enable(struct udevice *pmic, int ldo, bool enable)
|
{
|
uint mask;
|
int ret;
|
|
if (ldo < 5)
|
mask = 1 << (ldo + 1);
|
else
|
mask = 1;
|
ret = pmic_clrsetbits(pmic, RK806_PLDO_SUSPEND_EN, mask,
|
enable ? mask : 0);
|
|
return ret;
|
}
|
|
static int _pldo_get_suspend_enable(struct udevice *pmic, int ldo)
|
{
|
uint mask, val;
|
int ret;
|
|
if (ldo < 5)
|
mask = 1 << (ldo + 1);
|
else
|
mask = 1;
|
val = pmic_reg_read(pmic, RK806_PLDO_SUSPEND_EN);
|
|
if (val < 0)
|
return val;
|
ret = val & mask ? 1 : 0;
|
|
return ret;
|
}
|
|
static int pldo_set_suspend_enable(struct udevice *dev, bool enable)
|
{
|
int ldo = dev->driver_data - 1;
|
|
return _pldo_set_suspend_enable(dev->parent, ldo, enable);
|
}
|
|
static int pldo_get_suspend_enable(struct udevice *dev)
|
{
|
int ldo = dev->driver_data - 1;
|
|
return _pldo_get_suspend_enable(dev->parent, ldo);
|
}
|
|
static int rk8xx_buck_probe(struct udevice *dev)
|
{
|
struct dm_regulator_uclass_platdata *uc_pdata;
|
|
uc_pdata = dev_get_uclass_platdata(dev);
|
uc_pdata->type = REGULATOR_TYPE_BUCK;
|
uc_pdata->mode_count = 0;
|
|
return 0;
|
}
|
|
static int rk8xx_ldo_probe(struct udevice *dev)
|
{
|
struct dm_regulator_uclass_platdata *uc_pdata;
|
|
uc_pdata = dev_get_uclass_platdata(dev);
|
uc_pdata->type = REGULATOR_TYPE_LDO;
|
uc_pdata->mode_count = 0;
|
|
return 0;
|
}
|
|
static int rk8xx_pldo_probe(struct udevice *dev)
|
{
|
struct dm_regulator_uclass_platdata *uc_pdata;
|
|
uc_pdata = dev_get_uclass_platdata(dev);
|
uc_pdata->type = REGULATOR_TYPE_LDO;
|
uc_pdata->mode_count = 0;
|
|
return 0;
|
}
|
|
static const struct dm_regulator_ops rk8xx_buck_ops = {
|
.get_value = buck_get_value,
|
.set_value = buck_set_value,
|
.set_suspend_value = buck_set_suspend_value,
|
.get_suspend_value = buck_get_suspend_value,
|
.get_enable = buck_get_enable,
|
.set_enable = buck_set_enable,
|
.set_suspend_enable = buck_set_suspend_enable,
|
.get_suspend_enable = buck_get_suspend_enable,
|
.set_ramp_delay = buck_set_ramp_delay,
|
};
|
|
static const struct dm_regulator_ops rk8xx_ldo_ops = {
|
.get_value = ldo_get_value,
|
.set_value = ldo_set_value,
|
.set_suspend_value = ldo_set_suspend_value,
|
.get_suspend_value = ldo_get_suspend_value,
|
.get_enable = ldo_get_enable,
|
.set_enable = ldo_set_enable,
|
.set_suspend_enable = ldo_set_suspend_enable,
|
.get_suspend_enable = ldo_get_suspend_enable,
|
};
|
|
static const struct dm_regulator_ops rk8xx_pldo_ops = {
|
.get_value = pldo_get_value,
|
.set_value = pldo_set_value,
|
.set_suspend_value = pldo_set_suspend_value,
|
.get_suspend_value = pldo_get_suspend_value,
|
.get_enable = pldo_get_enable,
|
.set_enable = pldo_set_enable,
|
.set_suspend_enable = pldo_set_suspend_enable,
|
.get_suspend_enable = pldo_get_suspend_enable,
|
};
|
|
U_BOOT_DRIVER(rk8xx_spi_buck) = {
|
.name = "rk8xx_spi_buck",
|
.id = UCLASS_REGULATOR,
|
.ops = &rk8xx_buck_ops,
|
.probe = rk8xx_buck_probe,
|
};
|
|
U_BOOT_DRIVER(rk8xx_spi_ldo) = {
|
.name = "rk8xx_spi_ldo",
|
.id = UCLASS_REGULATOR,
|
.ops = &rk8xx_ldo_ops,
|
.probe = rk8xx_ldo_probe,
|
};
|
|
U_BOOT_DRIVER(rk8xx_spi_pldo) = {
|
.name = "rk8xx_spi_pldo",
|
.id = UCLASS_REGULATOR,
|
.ops = &rk8xx_pldo_ops,
|
.probe = rk8xx_pldo_probe,
|
};
|
#endif
|
