Overview
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--------
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The T1040RDB is a Freescale reference board that hosts the T1040 SoC
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(and variants). Variants inclued T1042 presonality of T1040, in which
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case T1040RDB can also be called T1042RDB.
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The T1042RDB is a Freescale reference board that hosts the T1042 SoC
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(and variants). The board is similar to T1040RDB, T1040 is a reduced
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personality of T1040 SoC without Integrated 8-port Gigabit(L2 Switch).
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The T1042RDB_PI is a Freescale reference board that hosts the T1042 SoC.
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(a personality of T1040 SoC). The board is similar to T1040RDB but is
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designed specially with low power features targeted for Printing Image Market.
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The T1040D4RDB is a Freescale reference board that hosts the T1040 SoC.
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The board is re-designed T1040RDB board with following changes :
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- Support of DDR4 memory and some enhancements
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The T1042D4RDB is a Freescale reference board that hosts the T1042 SoC.
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The board is re-designed T1040RDB board with following changes :
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- Support of DDR4 memory
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- Support for 0x86 serdes protocol which can support following interfaces
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- 2 RGMII's on DTSEC4, DTSEC5
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- 3 SGMII on DTSEC1, DTSEC2 & DTSEC3
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Basic difference's among T1040RDB, T1042RDB_PI, T1042RDB
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-------------------------------------------------------------------------
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Board Si Protocol Targeted Market
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-------------------------------------------------------------------------
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T1040RDB T1040 0x66 Networking
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T1040RDB T1042 0x86 Networking
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T1042RDB_PI T1042 0x06 Printing & Imaging
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T1040D4RDB T1040 0x66 Networking
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T1042D4RDB T1042 0x86 Networking
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T1040 SoC Overview
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------------------
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The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
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processor cores with high-performance data path acceleration architecture
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and network peripheral interfaces required for networking & telecommunications.
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The T1040/T1042 SoC includes the following function and features:
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- Four e5500 cores, each with a private 256 KB L2 cache
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- 256 KB shared L3 CoreNet platform cache (CPC)
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- Interconnect CoreNet platform
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- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
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support
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- Data Path Acceleration Architecture (DPAA) incorporating acceleration
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for the following functions:
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- Packet parsing, classification, and distribution
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- Queue management for scheduling, packet sequencing, and congestion
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management
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- Cryptography Acceleration (SEC 5.0)
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- RegEx Pattern Matching Acceleration (PME 2.2)
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- IEEE Std 1588 support
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- Hardware buffer management for buffer allocation and deallocation
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- Ethernet interfaces
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- Integrated 8-port Gigabit Ethernet switch (T1040 only)
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- Four 1 Gbps Ethernet controllers
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- Two RGMII interfaces or one RGMII and one MII interfaces
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- High speed peripheral interfaces
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- Four PCI Express 2.0 controllers running at up to 5 GHz
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- Two SATA controllers supporting 1.5 and 3.0 Gb/s operation
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- Upto two QSGMII interface
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- Upto six SGMII interface supporting 1000 Mbps
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- One SGMII interface supporting upto 2500 Mbps
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- Additional peripheral interfaces
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- Two USB 2.0 controllers with integrated PHY
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- SD/eSDHC/eMMC
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- eSPI controller
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- Four I2C controllers
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- Four UARTs
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- Four GPIO controllers
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- Integrated flash controller (IFC)
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- LCD and HDMI interface (DIU) with 12 bit dual data rate
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- TDM interface
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- Multicore programmable interrupt controller (PIC)
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- Two 8-channel DMA engines
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- Single source clocking implementation
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- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
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T1040 SoC Personalities
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-------------------------
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T1022 Personality:
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T1022 is a reduced personality of T1040 with less core/clusters.
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T1042 Personality:
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T1042 is a reduced personality of T1040 without Integrated 8-port Gigabit
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Ethernet switch. Rest of the blocks are same as T1040
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T1040RDB board Overview
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-------------------------
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- SERDES Connections, 8 lanes information:
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1: None
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2: SGMII
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3: QSGMII
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4: QSGMII
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5: PCIe1 x1 slot
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6: mini PCIe connector
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7: mini PCIe connector
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8: SATA connector
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- DDR Controller
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- Supports rates of up to 1600 MHz data-rate
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- Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
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- IFC/Local Bus
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- NAND flash: 1GB 8-bit NAND flash
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- NOR: 128MB 16-bit NOR Flash
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- Ethernet
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- Two on-board RGMII 10/100/1G ethernet ports.
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- CPLD
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- Clocks
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- System and DDR clock (SYSCLK, “DDRCLK”)
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- SERDES clocks
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- Power Supplies
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- USB
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- Supports two USB 2.0 ports with integrated PHYs
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- Two type A ports with 5V@1.5A per port.
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- SDHC
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- SDHC/SDXC connector
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- SPI
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- On-board 64MB SPI flash
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- Other IO
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- Two Serial ports
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- Four I2C ports
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T1042RDB_PI board Overview
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-------------------------
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- SERDES Connections, 8 lanes information:
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1, 2, 3, 4 : PCIe x4 slot
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5: mini PCIe connector
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6: mini PCIe connector
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7: NA
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8: SATA connector
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- DDR Controller
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- Supports rates of up to 1600 MHz data-rate
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- Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
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- IFC/Local Bus
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- NAND flash: 1GB 8-bit NAND flash
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- NOR: 128MB 16-bit NOR Flash
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- Ethernet
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- Two on-board RGMII 10/100/1G ethernet ports.
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- CPLD
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- Clocks
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- System and DDR clock (SYSCLK, “DDRCLK”)
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- SERDES clocks
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- Video
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- DIU supports video at up to 1280x1024x32bpp
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- Power Supplies
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- USB
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- Supports two USB 2.0 ports with integrated PHYs
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- Two type A ports with 5V@1.5A per port.
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- SDHC
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- SDHC/SDXC connector
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- SPI
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- On-board 64MB SPI flash
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- Other IO
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- Two Serial ports
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- Four I2C ports
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Memory map
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-----------
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The addresses in brackets are physical addresses.
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Start Address End Address Description Size
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0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
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0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
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0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
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0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB
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0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
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0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
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0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
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0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
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0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
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0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
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0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
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0xC_3000_0000 0xC_3FFF_FFFF PCI Express 4 Mem Space 256MB
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0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB
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0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB
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0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB
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0x0_0000_0000 0x0_ffff_ffff DDR 2GB
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NOR Flash memory Map
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---------------------
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Start End Definition Size
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0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB
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0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB
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0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
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0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
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0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
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0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
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0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
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0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB
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0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB
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0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
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0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
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0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB
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0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
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0xE8000000 0xE801FFFF RCW (current bank) 128KB
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Various Software configurations/environment variables/commands
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--------------------------------------------------------------
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The below commands apply to the board
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1. U-Boot environment variable hwconfig
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The default hwconfig is:
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hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1:
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dr_mode=host,phy_type=utmi
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Note: For USB gadget set "dr_mode=peripheral"
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2. FMAN Ucode versions
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fsl_fman_ucode_t1040.bin
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3. Switching to alternate bank
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Commands for switching to alternate bank.
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1. To change from vbank0 to vbank4
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=> cpld reset altbank (it will boot using vbank4)
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2.To change from vbank4 to vbank0
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=> cpld reset (it will boot using vbank0)
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NAND boot with 2 Stage boot loader
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----------------------------------
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PBL initialise the internal SRAM and copy SPL(160KB) in SRAM.
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SPL further initialise DDR using SPD and environment variables and copy
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U-Boot(768 KB) from flash to DDR.
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Finally SPL transer control to U-Boot for futher booting.
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SPL has following features:
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- Executes within 256K
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- No relocation required
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Run time view of SPL framework during boot :-
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-----------------------------------------------
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Area | Address |
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-----------------------------------------------
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Secure boot | 0xFFFC0000 (32KB) |
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headers | |
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-----------------------------------------------
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GD, BD | 0xFFFC8000 (4KB) |
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-----------------------------------------------
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ENV | 0xFFFC9000 (8KB) |
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-----------------------------------------------
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HEAP | 0xFFFCB000 (30KB) |
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-----------------------------------------------
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STACK | 0xFFFD8000 (22KB) |
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-----------------------------------------------
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U-Boot SPL | 0xFFFD8000 (160KB) |
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-----------------------------------------------
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NAND Flash memory Map on T104xRDB
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------------------------------------------
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Start End Definition Size
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0x000000 0x0FFFFF U-Boot 1MB
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0x180000 0x19FFFF U-Boot env 128KB
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0x280000 0x29FFFF FMAN Ucode 128KB
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0x380000 0x39FFFF QE Firmware 128KB
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SD Card memory Map on T104xRDB
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------------------------------------------
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Block #blocks Definition Size
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0x008 2048 U-Boot 1MB
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0x800 0024 U-Boot env 8KB
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0x820 0256 FMAN Ucode 128KB
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0x920 0256 QE Firmware 128KB
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SPI Flash memory Map on T104xRDB
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------------------------------------------
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Start End Definition Size
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0x000000 0x0FFFFF U-Boot 1MB
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0x100000 0x101FFF U-Boot env 8KB
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0x110000 0x12FFFF FMAN Ucode 128KB
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0x130000 0x14FFFF QE Firmware 128KB
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Please note QE Firmware is only valid for T1040RDB
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Switch Settings for T104xRDB boards: (ON is 0, OFF is 1)
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==========================================================
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NOR boot SW setting:
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SW1: 00010011
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SW2: 10111011
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SW3: 11100001
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NAND boot SW setting:
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SW1: 10001000
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SW2: 00111011
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SW3: 11110001
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SPI boot SW setting:
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SW1: 00100010
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SW2: 10111011
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SW3: 11100001
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SD boot SW setting:
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SW1: 00100000
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SW2: 00111011
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SW3: 11100001
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Switch Settings for T104xD4RDB boards: (ON is 0, OFF is 1)
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=============================================================
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NOR boot SW setting:
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SW1: 00010011
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SW2: 10111001
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SW3: 11100001
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NAND boot SW setting:
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SW1: 10001000
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SW2: 00111001
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SW3: 11110001
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SPI boot SW setting:
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SW1: 00100010
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SW2: 10111001
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SW3: 11100001
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SD boot SW setting:
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SW1: 00100000
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SW2: 00111001
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SW3: 11100001
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PBL-based image generation
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==========================
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Changes only the required register bit in in PBI commands.
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Provides reference code which might needs some
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modification as per requirement.
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example:
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By default PBI_SRC=14 (which is for IFC-NAND/NOR) in rcw.cfg file
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which needs to be changed for SPI and SD.
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For SD-boot
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==============
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1. Set RCW[192:195], PBI_SRC bits as 6 in RCW file (t1040d4_rcw.cfg type files)
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example:
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RCW file: board/freescale/t104xrdb/t1040d4_rcw.cfg
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Change
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66000002 40000002 ec027000 01000000
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to
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66000002 40000002 6c027000 01000000
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2. SD does not support flush so remove flush from pbl, make changes in
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tools/pblimage.c file, Update value of pbl_end_cmd[0] = 0x09138000
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with 0x091380c0
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For SPI-boot
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==============
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1. Set RCW[192:195], PBI_SRC bits as 5 in RCW file (t1040d4_rcw.cfg type files)
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example:
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RCW file: board/freescale/t104xrdb/t1040d4_rcw.cfg
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Change
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66000002 40000002 ec027000 01000000
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to
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66000002 40000002 5c027000 01000000
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2. SPI does not support flush so remove flush from pbl, make changes in
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tools/pblimage.c file, Update value of pbl_end_cmd[0] = 0x09138000
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with 0x091380c0
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