Overview
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--------
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QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
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development platform, with a complete debugging environment.
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The LS1012ARDB board supports the QorIQ LS1012A processor and is
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optimized to support the high-bandwidth DDR3L memory and
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a full complement of high-speed SerDes ports.
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LS1012A SoC Overview
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--------------------
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Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
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SoC overview.
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LS1012ARDB board Overview
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-----------------------
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- SERDES Connections, 4 lanes supporting:
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- PCI Express - 3.0
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- SGMII, SGMII 2.5
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- SATA 3.0
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- DDR Controller
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- 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
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-QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
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signals to
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- QSPI NOR flash memory (2 virtual banks)
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- the QSPI emulator.s
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- USB 3.0
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- one high-speed USB 2.0/3.0 port.
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- Two enhanced secure digital host controllers:
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- SDHC1 controller can be connected to onboard SDHC connector
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- SDHC2 controller: Three dual 1:4 mux/demux devices,
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74CBTLV3253DS (U30, U31, U33) drive the SDHC2 signals to eMMC,
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SDIO WiFi, SPI, and Ardiuno shield
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- 2 I2C controllers
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- One SATA onboard connectors
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- UART
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- The LS1012A processor consists of two UART controllers,
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out of which only UART1 is used on RDB.
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- ARM JTAG support
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Booting Options
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---------------
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a) QSPI Flash Emu Boot
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b) QSPI Flash 1
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c) QSPI Flash 2
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QSPI flash map
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--------------
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Images | Size |QSPI Flash Address
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------------------------------------------
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RCW + PBI | 1MB | 0x4000_0000
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U-boot | 1MB | 0x4010_0000
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U-boot Env | 1MB | 0x4020_0000
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PPA FIT image | 2MB | 0x4050_0000
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Linux ITB | ~53MB | 0x40A0_0000
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