/*
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* armboot - Startup Code for ARM926EJS CPU-core
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*
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* Copyright (c) 2003 Texas Instruments
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*
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* ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
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*
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* Copyright (c) 2001 Marius Groger <mag@sysgo.de>
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* Copyright (c) 2002 Alex Zupke <azu@sysgo.de>
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* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
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* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
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* Copyright (c) 2003 Kshitij <kshitij@ti.com>
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* Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net>
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*
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* Change to support call back into iMX28 bootrom
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* Copyright (c) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <common.h>
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/*
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*************************************************************************
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*
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* Startup Code (reset vector)
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*
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* do important init only if we don't start from memory!
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* setup Memory and board specific bits prior to relocation.
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* relocate armboot to ram
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* setup stack
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*
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*************************************************************************
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*/
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.globl reset
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reset:
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/*
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* If the CPU is configured in "Wait JTAG connection mode", the stack
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* pointer is not configured and is zero. This will cause crash when
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* trying to push data onto stack right below here. Load the SP and make
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* it point to the end of OCRAM if the SP is zero.
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*/
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cmp sp, #0x00000000
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ldreq sp, =CONFIG_SYS_INIT_SP_ADDR
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/*
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* Store all registers on old stack pointer, this will allow us later to
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* return to the BootROM and let the BootROM load U-Boot into RAM.
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*
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* WARNING: Register r0 and r1 are used by the BootROM to pass data
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* to the called code. Register r0 will contain arbitrary
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* data that are set in the BootStream. In case this code
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* was started with CALL instruction, register r1 will contain
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* pointer to the return value this function can then set.
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* The code below MUST NOT CHANGE register r0 and r1 !
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*/
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push {r0-r12,r14}
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/* Save control register c1 */
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mrc p15, 0, r2, c1, c0, 0
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push {r2}
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/* Set the cpu to SVC32 mode and store old CPSR register content. */
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mrs r2, cpsr
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push {r2}
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bic r2, r2, #0x1f
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orr r2, r2, #0xd3
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msr cpsr, r2
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bl board_init_ll
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/* Restore BootROM's CPU mode (especially FIQ). */
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pop {r2}
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msr cpsr,r2
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/*
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* Restore c1 register. Especially set exception vector location
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* back to BootROM space which is required by bootrom for USB boot.
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*/
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pop {r2}
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mcr p15, 0, r2, c1, c0, 0
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pop {r0-r12,r14}
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/*
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* In case this code was started by the CALL instruction, the register
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* r0 is examined by the BootROM after this code returns. The value in
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* r0 must be set to 0 to indicate successful return.
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*/
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mov r0, #0
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bx lr
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