/*
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*************************************************************************
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* Rockchip driver for CIF ISP 1.0
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* (Based on Intel driver for sofiaxxx)
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*
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* Copyright (C) 2015 Intel Mobile Communications GmbH
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* Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*************************************************************************
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*/
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#ifndef _CIF_ISP10_PLATFORM_H
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#define _CIF_ISP10_PLATFORM_H
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#include <linux/videodev2.h>
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#define CIF_ISP10_SOC_RK3288 "rk3288"
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#define CIF_ISP10_SOC_RK3368 "rk3368"
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#define CIF_ISP10_SOC_RK3399 "rk3399"
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#define DRIVER_NAME "rkisp10"
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#define ISP_VDEV_NAME DRIVER_NAME "_ispdev"
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#define SP_VDEV_NAME DRIVER_NAME "_selfpath"
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#define MP_VDEV_NAME DRIVER_NAME "_mainpath"
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#define DMA_VDEV_NAME DRIVER_NAME "_dmapath"
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enum pltfrm_cam_signal_polarity {
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PLTFRM_CAM_SIGNAL_HIGH_LEVEL = 0,
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PLTFRM_CAM_SIGNAL_LOW_LEVEL = 1,
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};
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enum pltfrm_cam_sample_type {
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PLTFRM_CAM_SDR_NEG_EDG = 0x10000001,
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PLTFRM_CAM_SDR_POS_EDG = 0x10000002,
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PLTFRM_CAM_DDR = 0x20000000
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};
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enum pltfrm_cam_itf_type {
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PLTFRM_CAM_ITF_MIPI = 0x10000000,
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PLTFRM_CAM_ITF_BT601_8 = 0x20000071,
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PLTFRM_CAM_ITF_BT656_8 = 0x20000072,
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PLTFRM_CAM_ITF_BT601_10 = 0x20000091,
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PLTFRM_CAM_ITF_BT656_10 = 0x20000092,
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PLTFRM_CAM_ITF_BT601_12 = 0x200000B1,
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PLTFRM_CAM_ITF_BT656_12 = 0x200000B2,
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PLTFRM_CAM_ITF_BT601_16 = 0x200000F1,
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PLTFRM_CAM_ITF_BT656_16 = 0x200000F2,
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PLTFRM_CAM_ITF_BT656_8I = 0x20000172
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};
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#define PLTFRM_CAM_ITF_MAIN_MASK 0xf0000000
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#define PLTFRM_CAM_ITF_SUB_MASK 0x0000000f
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#define PLTFRM_CAM_ITF_DVP_BW_MASK 0x000000f0
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#define PLTFRM_CAM_ITF_INTERLACE_MASK 0x00000100
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#define PLTFRM_CAM_ITF_IS_MIPI(a) \
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(((a) & PLTFRM_CAM_ITF_MAIN_MASK) == 0x10000000)
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#define PLTFRM_CAM_ITF_IS_DVP(a) \
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(((a) & PLTFRM_CAM_ITF_MAIN_MASK) == 0x20000000)
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#define PLTFRM_CAM_ITF_IS_BT656(a) (PLTFRM_CAM_ITF_IS_DVP(a) &&\
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(((a) & PLTFRM_CAM_ITF_SUB_MASK) == 0x02))
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#define PLTFRM_CAM_ITF_IS_BT601(a) (PLTFRM_CAM_ITF_IS_DVP(a) &&\
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(((a) & PLTFRM_CAM_ITF_SUB_MASK) == 0x01))
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#define PLTFRM_CAM_ITF_DVP_BW(a) \
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((((a) & PLTFRM_CAM_ITF_DVP_BW_MASK) >> 4) + 1)
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#define PLTFRM_CAM_ITF_INTERLACE(a) \
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(((a) & PLTFRM_CAM_ITF_INTERLACE_MASK) == 0x00000100)
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struct pltfrm_cam_mipi_config {
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u32 dphy_index;
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u32 vc;
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u32 nb_lanes;
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u32 bit_rate;
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};
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struct pltfrm_cam_dvp_config {
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enum pltfrm_cam_signal_polarity vsync;
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enum pltfrm_cam_signal_polarity hsync;
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enum pltfrm_cam_sample_type pclk;
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};
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struct pltfrm_cam_itf {
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enum pltfrm_cam_itf_type type;
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union {
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struct pltfrm_cam_mipi_config mipi;
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struct pltfrm_cam_dvp_config dvp;
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} cfg;
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unsigned int mclk_hz;
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};
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#define PLTFRM_CAM_ITF_MIPI_CFG(v, nb, br, mk)\
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.itf_cfg = {\
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.type = PLTFRM_CAM_ITF_MIPI,\
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.cfg = {\
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.mipi = {\
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.dphy_index = 0,\
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.vc = v,\
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.nb_lanes = nb,\
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.bit_rate = br,\
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} \
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},\
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.mclk_hz = mk\
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}
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#define PLTFRM_CAM_ITF_DVP_CFG(ty, vs, hs, ck, mk)\
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.itf_cfg = {\
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.type = ty,\
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.cfg = {\
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.dvp = {\
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.vsync = vs,\
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.hsync = hs,\
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.pclk = ck,\
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} \
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},\
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.mclk_hz = mk\
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}
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#define PLTFRM_CIFCAM_IOCTL_INTERNAL_BASE 0x00
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#define PLTFRM_CIFCAM_G_ITF_CFG \
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(PLTFRM_CIFCAM_IOCTL_INTERNAL_BASE + 1)
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#define PLTFRM_CIFCAM_G_DEFRECT \
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(PLTFRM_CIFCAM_IOCTL_INTERNAL_BASE + 2)
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#define PLTFRM_CIFCAM_ATTACH \
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(PLTFRM_CIFCAM_IOCTL_INTERNAL_BASE + 3)
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#define PLTFRM_CIFCAM_SET_VCM_POS \
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(PLTFRM_CIFCAM_IOCTL_INTERNAL_BASE + 4)
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#define PLTFRM_CIFCAM_GET_VCM_POS \
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(PLTFRM_CIFCAM_IOCTL_INTERNAL_BASE + 5)
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#define PLTFRM_CIFCAM_GET_VCM_MOVE_RES \
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(PLTFRM_CIFCAM_IOCTL_INTERNAL_BASE + 6)
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struct pltfrm_cam_vcm_tim {
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struct timeval vcm_start_t;
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struct timeval vcm_end_t;
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};
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struct pltfrm_cam_defrect {
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unsigned int width;
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unsigned int height;
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struct v4l2_rect defrect;
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};
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enum pltfrm_soc_cfg_cmd {
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PLTFRM_MCLK_CFG = 0,
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PLTFRM_MIPI_DPHY_CFG,
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PLTFRM_CLKEN,
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PLTFRM_CLKDIS,
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PLTFRM_CLKRST,
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PLTFRM_SOC_INIT
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};
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enum pltfrm_soc_io_voltage {
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PLTFRM_IO_1V8 = 0,
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PLTFRM_IO_3V3 = 1
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};
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enum pltfrm_soc_drv_strength {
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PLTFRM_DRV_STRENGTH_0 = 0,
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PLTFRM_DRV_STRENGTH_1 = 1,
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PLTFRM_DRV_STRENGTH_2 = 2,
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PLTFRM_DRV_STRENGTH_3 = 3
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};
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struct pltfrm_soc_init_para {
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struct platform_device *pdev;
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void __iomem *isp_base;
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};
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struct pltfrm_soc_mclk_para {
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enum pltfrm_soc_io_voltage io_voltage;
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enum pltfrm_soc_drv_strength drv_strength;
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};
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struct pltfrm_soc_cfg_para {
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enum pltfrm_soc_cfg_cmd cmd;
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void **isp_config;
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void *cfg_para;
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};
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struct pltfrm_soc_cfg {
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char name[32];
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void *isp_config;
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int (*soc_cfg)(struct pltfrm_soc_cfg_para *cfg);
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};
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int pltfrm_rk3288_cfg(struct pltfrm_soc_cfg_para *cfg);
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int pltfrm_rk3399_cfg(struct pltfrm_soc_cfg_para *cfg);
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#endif
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