// SPDX-License-Identifier: GPL-2.0
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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******************************************************************************/
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#include "odm_precomp.h"
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#include "phy.h"
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static void dm_rx_hw_antena_div_init(struct odm_dm_struct *dm_odm)
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{
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struct adapter *adapter = dm_odm->Adapter;
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u32 value32;
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if (*(dm_odm->mp_mode) == 1) {
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dm_odm->AntDivType = CGCS_RX_SW_ANTDIV;
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phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT(7), 0);
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phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(31), 1);
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return;
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}
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/* MAC Setting */
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value32 = phy_query_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
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phy_set_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord,
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value32|(BIT(23) | BIT(25)));
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/* Pin Settings */
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phy_set_bb_reg(adapter, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);
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phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0);
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phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(22), 1);
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phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(31), 1);
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/* OFDM Settings */
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phy_set_bb_reg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord,
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0x000000a0);
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/* CCK Settings */
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phy_set_bb_reg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1);
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phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1);
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rtl88eu_dm_update_rx_idle_ant(dm_odm, MAIN_ANT);
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phy_set_bb_reg(adapter, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0201);
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}
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static void dm_trx_hw_antenna_div_init(struct odm_dm_struct *dm_odm)
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{
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struct adapter *adapter = dm_odm->Adapter;
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u32 value32;
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if (*(dm_odm->mp_mode) == 1) {
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dm_odm->AntDivType = CGCS_RX_SW_ANTDIV;
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phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT(7), 0);
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phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,
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BIT(5) | BIT(4) | BIT(3), 0);
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return;
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}
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/* MAC Setting */
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value32 = phy_query_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
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phy_set_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord,
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value32|(BIT(23) | BIT(25)));
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/* Pin Settings */
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phy_set_bb_reg(adapter, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);
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phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0);
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phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(22), 0);
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phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(31), 1);
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/* OFDM Settings */
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phy_set_bb_reg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord,
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0x000000a0);
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/* CCK Settings */
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phy_set_bb_reg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1);
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phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1);
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/* Tx Settings */
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phy_set_bb_reg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT(21), 0);
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rtl88eu_dm_update_rx_idle_ant(dm_odm, MAIN_ANT);
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/* antenna mapping table */
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if (!dm_odm->bIsMPChip) { /* testchip */
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phy_set_bb_reg(adapter, ODM_REG_RX_DEFAULT_A_11N,
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BIT(10) | BIT(9) | BIT(8), 1);
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phy_set_bb_reg(adapter, ODM_REG_RX_DEFAULT_A_11N,
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BIT(13) | BIT(12) | BIT(11), 2);
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} else { /* MPchip */
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phy_set_bb_reg(adapter, ODM_REG_ANT_MAPPING1_11N, bMaskDWord,
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0x0201);
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}
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}
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static void dm_fast_training_init(struct odm_dm_struct *dm_odm)
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{
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struct adapter *adapter = dm_odm->Adapter;
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u32 value32, i;
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struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
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u32 AntCombination = 2;
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if (*(dm_odm->mp_mode) == 1) {
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return;
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}
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for (i = 0; i < 6; i++) {
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dm_fat_tbl->Bssid[i] = 0;
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dm_fat_tbl->antSumRSSI[i] = 0;
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dm_fat_tbl->antRSSIcnt[i] = 0;
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dm_fat_tbl->antAveRSSI[i] = 0;
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}
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dm_fat_tbl->TrainIdx = 0;
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dm_fat_tbl->FAT_State = FAT_NORMAL_STATE;
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/* MAC Setting */
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value32 = phy_query_bb_reg(adapter, 0x4c, bMaskDWord);
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phy_set_bb_reg(adapter, 0x4c, bMaskDWord, value32|(BIT(23) | BIT(25)));
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value32 = phy_query_bb_reg(adapter, 0x7B4, bMaskDWord);
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phy_set_bb_reg(adapter, 0x7b4, bMaskDWord, value32|(BIT(16) | BIT(17)));
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/* Match MAC ADDR */
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phy_set_bb_reg(adapter, 0x7b4, 0xFFFF, 0);
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phy_set_bb_reg(adapter, 0x7b0, bMaskDWord, 0);
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phy_set_bb_reg(adapter, 0x870, BIT(9) | BIT(8), 0);
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phy_set_bb_reg(adapter, 0x864, BIT(10), 0);
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phy_set_bb_reg(adapter, 0xb2c, BIT(22), 0);
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phy_set_bb_reg(adapter, 0xb2c, BIT(31), 1);
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phy_set_bb_reg(adapter, 0xca4, bMaskDWord, 0x000000a0);
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/* antenna mapping table */
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if (AntCombination == 2) {
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if (!dm_odm->bIsMPChip) { /* testchip */
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phy_set_bb_reg(adapter, 0x858, BIT(10) | BIT(9) | BIT(8), 1);
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phy_set_bb_reg(adapter, 0x858, BIT(13) | BIT(12) | BIT(11), 2);
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} else { /* MPchip */
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phy_set_bb_reg(adapter, 0x914, bMaskByte0, 1);
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phy_set_bb_reg(adapter, 0x914, bMaskByte1, 2);
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}
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} else if (AntCombination == 7) {
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if (!dm_odm->bIsMPChip) { /* testchip */
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phy_set_bb_reg(adapter, 0x858, BIT(10) | BIT(9) | BIT(8), 0);
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phy_set_bb_reg(adapter, 0x858, BIT(13) | BIT(12) | BIT(11), 1);
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phy_set_bb_reg(adapter, 0x878, BIT(16), 0);
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phy_set_bb_reg(adapter, 0x858, BIT(15) | BIT(14), 2);
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phy_set_bb_reg(adapter, 0x878, BIT(19) | BIT(18) | BIT(17), 3);
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phy_set_bb_reg(adapter, 0x878, BIT(22) | BIT(21) | BIT(20), 4);
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phy_set_bb_reg(adapter, 0x878, BIT(25) | BIT(24) | BIT(23), 5);
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phy_set_bb_reg(adapter, 0x878, BIT(28) | BIT(27) | BIT(26), 6);
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phy_set_bb_reg(adapter, 0x878, BIT(31) | BIT(30) | BIT(29), 7);
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} else { /* MPchip */
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phy_set_bb_reg(adapter, 0x914, bMaskByte0, 0);
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phy_set_bb_reg(adapter, 0x914, bMaskByte1, 1);
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phy_set_bb_reg(adapter, 0x914, bMaskByte2, 2);
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phy_set_bb_reg(adapter, 0x914, bMaskByte3, 3);
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phy_set_bb_reg(adapter, 0x918, bMaskByte0, 4);
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phy_set_bb_reg(adapter, 0x918, bMaskByte1, 5);
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phy_set_bb_reg(adapter, 0x918, bMaskByte2, 6);
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phy_set_bb_reg(adapter, 0x918, bMaskByte3, 7);
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}
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}
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/* Default Ant Setting when no fast training */
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phy_set_bb_reg(adapter, 0x80c, BIT(21), 1);
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phy_set_bb_reg(adapter, 0x864, BIT(5) | BIT(4) | BIT(3), 0);
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phy_set_bb_reg(adapter, 0x864, BIT(8) | BIT(7) | BIT(6), 1);
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/* Enter Traing state */
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phy_set_bb_reg(adapter, 0x864, BIT(2) | BIT(1) | BIT(0), (AntCombination-1));
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phy_set_bb_reg(adapter, 0xc50, BIT(7), 1);
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}
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void rtl88eu_dm_antenna_div_init(struct odm_dm_struct *dm_odm)
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{
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if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV)
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dm_rx_hw_antena_div_init(dm_odm);
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else if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
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dm_trx_hw_antenna_div_init(dm_odm);
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else if (dm_odm->AntDivType == CG_TRX_SMART_ANTDIV)
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dm_fast_training_init(dm_odm);
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}
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void rtl88eu_dm_update_rx_idle_ant(struct odm_dm_struct *dm_odm, u8 ant)
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{
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struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
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struct adapter *adapter = dm_odm->Adapter;
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u32 default_ant, optional_ant;
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if (dm_fat_tbl->RxIdleAnt != ant) {
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if (ant == MAIN_ANT) {
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default_ant = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ?
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MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX;
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optional_ant = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ?
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AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX;
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} else {
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default_ant = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ?
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AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX;
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optional_ant = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ?
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MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX;
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}
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if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) {
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phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,
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BIT(5) | BIT(4) | BIT(3), default_ant);
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phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,
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BIT(8) | BIT(7) | BIT(6), optional_ant);
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phy_set_bb_reg(adapter, ODM_REG_ANTSEL_CTRL_11N,
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BIT(14) | BIT(13) | BIT(12), default_ant);
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phy_set_bb_reg(adapter, ODM_REG_RESP_TX_11N,
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BIT(6) | BIT(7), default_ant);
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} else if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV) {
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phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,
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BIT(5) | BIT(4) | BIT(3), default_ant);
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phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,
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BIT(8) | BIT(7) | BIT(6), optional_ant);
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}
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}
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dm_fat_tbl->RxIdleAnt = ant;
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}
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static void update_tx_ant_88eu(struct odm_dm_struct *dm_odm, u8 ant, u32 mac_id)
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{
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struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
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u8 target_ant;
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if (ant == MAIN_ANT)
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target_ant = MAIN_ANT_CG_TRX;
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else
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target_ant = AUX_ANT_CG_TRX;
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dm_fat_tbl->antsel_a[mac_id] = target_ant & BIT(0);
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dm_fat_tbl->antsel_b[mac_id] = (target_ant & BIT(1))>>1;
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dm_fat_tbl->antsel_c[mac_id] = (target_ant & BIT(2))>>2;
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}
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void rtl88eu_dm_set_tx_ant_by_tx_info(struct odm_dm_struct *dm_odm,
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u8 *desc, u8 mac_id)
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{
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struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
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if ((dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ||
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(dm_odm->AntDivType == CG_TRX_SMART_ANTDIV)) {
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SET_TX_DESC_ANTSEL_A_88E(desc, dm_fat_tbl->antsel_a[mac_id]);
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SET_TX_DESC_ANTSEL_B_88E(desc, dm_fat_tbl->antsel_b[mac_id]);
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SET_TX_DESC_ANTSEL_C_88E(desc, dm_fat_tbl->antsel_c[mac_id]);
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}
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}
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void rtl88eu_dm_ant_sel_statistics(struct odm_dm_struct *dm_odm,
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u8 antsel_tr_mux, u32 mac_id, u8 rx_pwdb_all)
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{
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struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
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if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) {
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if (antsel_tr_mux == MAIN_ANT_CG_TRX) {
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dm_fat_tbl->MainAnt_Sum[mac_id] += rx_pwdb_all;
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dm_fat_tbl->MainAnt_Cnt[mac_id]++;
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} else {
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dm_fat_tbl->AuxAnt_Sum[mac_id] += rx_pwdb_all;
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dm_fat_tbl->AuxAnt_Cnt[mac_id]++;
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}
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} else if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV) {
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if (antsel_tr_mux == MAIN_ANT_CGCS_RX) {
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dm_fat_tbl->MainAnt_Sum[mac_id] += rx_pwdb_all;
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dm_fat_tbl->MainAnt_Cnt[mac_id]++;
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} else {
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dm_fat_tbl->AuxAnt_Sum[mac_id] += rx_pwdb_all;
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dm_fat_tbl->AuxAnt_Cnt[mac_id]++;
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}
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}
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}
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static void rtl88eu_dm_hw_ant_div(struct odm_dm_struct *dm_odm)
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{
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struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
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struct rtw_dig *dig_table = &dm_odm->DM_DigTable;
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struct sta_info *entry;
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u32 i, min_rssi = 0xFF, ant_div_max_rssi = 0, max_rssi = 0;
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u32 local_min_rssi, local_max_rssi;
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u32 main_rssi, aux_rssi;
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u8 RxIdleAnt = 0, target_ant = 7;
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for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
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entry = dm_odm->pODM_StaInfo[i];
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if (IS_STA_VALID(entry)) {
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/* 2 Caculate RSSI per Antenna */
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main_rssi = (dm_fat_tbl->MainAnt_Cnt[i] != 0) ?
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(dm_fat_tbl->MainAnt_Sum[i]/dm_fat_tbl->MainAnt_Cnt[i]) : 0;
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aux_rssi = (dm_fat_tbl->AuxAnt_Cnt[i] != 0) ?
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(dm_fat_tbl->AuxAnt_Sum[i]/dm_fat_tbl->AuxAnt_Cnt[i]) : 0;
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target_ant = (main_rssi >= aux_rssi) ? MAIN_ANT : AUX_ANT;
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/* 2 Select max_rssi for DIG */
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local_max_rssi = max(main_rssi, aux_rssi);
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if ((local_max_rssi > ant_div_max_rssi) &&
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(local_max_rssi < 40))
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ant_div_max_rssi = local_max_rssi;
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if (local_max_rssi > max_rssi)
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max_rssi = local_max_rssi;
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/* 2 Select RX Idle Antenna */
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if ((dm_fat_tbl->RxIdleAnt == MAIN_ANT) &&
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(main_rssi == 0))
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main_rssi = aux_rssi;
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else if ((dm_fat_tbl->RxIdleAnt == AUX_ANT) &&
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(aux_rssi == 0))
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aux_rssi = main_rssi;
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local_min_rssi = min(main_rssi, aux_rssi);
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if (local_min_rssi < min_rssi) {
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min_rssi = local_min_rssi;
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RxIdleAnt = target_ant;
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}
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/* 2 Select TRX Antenna */
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if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
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update_tx_ant_88eu(dm_odm, target_ant, i);
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}
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dm_fat_tbl->MainAnt_Sum[i] = 0;
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dm_fat_tbl->AuxAnt_Sum[i] = 0;
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dm_fat_tbl->MainAnt_Cnt[i] = 0;
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dm_fat_tbl->AuxAnt_Cnt[i] = 0;
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}
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/* 2 Set RX Idle Antenna */
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rtl88eu_dm_update_rx_idle_ant(dm_odm, RxIdleAnt);
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dig_table->AntDiv_RSSI_max = ant_div_max_rssi;
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dig_table->RSSI_max = max_rssi;
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}
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void rtl88eu_dm_antenna_diversity(struct odm_dm_struct *dm_odm)
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{
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struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
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struct adapter *adapter = dm_odm->Adapter;
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if (!(dm_odm->SupportAbility & ODM_BB_ANT_DIV))
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return;
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if (!dm_odm->bLinked) {
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ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
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("ODM_AntennaDiversity_88E(): No Link.\n"));
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if (dm_fat_tbl->bBecomeLinked) {
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ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
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("Need to Turn off HW AntDiv\n"));
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phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT(7), 0);
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phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA1_11N,
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BIT(15), 0);
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if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
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phy_set_bb_reg(adapter, ODM_REG_TX_ANT_CTRL_11N,
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BIT(21), 0);
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dm_fat_tbl->bBecomeLinked = dm_odm->bLinked;
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}
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return;
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} else {
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if (!dm_fat_tbl->bBecomeLinked) {
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ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
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("Need to Turn on HW AntDiv\n"));
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phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT(7), 1);
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phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA1_11N,
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BIT(15), 1);
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if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
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phy_set_bb_reg(adapter, ODM_REG_TX_ANT_CTRL_11N,
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BIT(21), 1);
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dm_fat_tbl->bBecomeLinked = dm_odm->bLinked;
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}
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}
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if ((dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ||
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(dm_odm->AntDivType == CGCS_RX_HW_ANTDIV))
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rtl88eu_dm_hw_ant_div(dm_odm);
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}
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